Abstract: A computer system having a hierarchical bus structure that allows decoupling of a local bus from a global bus thereof. Decoupling of the local bus is achieved through use of an asynchronous system bus adapter which includes a local bus adapter for handling transactions, initiated by a system device coupled to the global bus, that require access to a local device coupled to the local bus and a global bus adapter for handling transactions, initiated by a local device coupled to the local bus, that require access to a system device coupled to the system bus. The local bus adapter is further configured to issue signals which prevent the global bus adapter from handling transactions initiated by local devices coupled to the local bus while transactions initiated by system devices coupled to the global bus are on-going.

Abstract: The present invention is an integrated circuit containing multiple digital signal processors (DSPs). A single host processor interface is also placed on the chip to connect the multiple DSPs to the host. A separate direct memory access (DMA) unit is provided for each DSP to facilitate flow of data to and from a data memory for each DSP. Each DSP also includes an instruction memory.

Abstract: In some embodiments, a system includes a memory device in a first clock domain region and a memory device and a digital signal processing (DSP) sub-system in a second clock domain region. In addition, a plurality of asynchronous first-in first-out (FIFO) data structures, each comprising a read interface, a write interface, and one or more data slots, store data generated from the DSP sub-system. The read interface operates in the first clock domain, and the write interface operates in the second clock domain.