Patents by Inventor Keith Dang

Keith Dang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060031619
    Abstract: A computer system having a hierarchical bus structure that allows decoupling of a local bus from a global bus thereof. Decoupling of the local bus is achieved through use of an asynchronous system bus adapter which includes a local bus adapter for handling transactions, initiated by a system device coupled to the global bus, that require access to a local device coupled to the local bus and a global bus adapter for handling transactions, initiated by a local device coupled to the local bus, that require access to a system device coupled to the system bus. The local bus adapter is further configured to issue signals which prevent the global bus adapter from handling transactions initiated by local devices coupled to the local bus while transactions initiated by system devices coupled to the global bus are on-going.
    Type: Application
    Filed: August 5, 2004
    Publication date: February 9, 2006
    Inventors: Hung Nguyen, Keith Dang
  • Patent number: 6959376
    Abstract: The present invention is an integrated circuit containing multiple digital signal processors (DSPs). A single host processor interface is also placed on the chip to connect the multiple DSPs to the host. A separate direct memory access (DMA) unit is provided for each DSP to facilitate flow of data to and from a data memory for each DSP. Each DSP also includes an instruction memory.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: October 25, 2005
    Assignee: LSI Logic Corporation
    Inventors: Mark Boike, Alan Phan, Keith Dang, Charles H. Stewart
  • Patent number: 6956788
    Abstract: In some embodiments, a system includes a memory device in a first clock domain region and a memory device and a digital signal processing (DSP) sub-system in a second clock domain region. In addition, a plurality of asynchronous first-in first-out (FIFO) data structures, each comprising a read interface, a write interface, and one or more data slots, store data generated from the DSP sub-system. The read interface operates in the first clock domain, and the write interface operates in the second clock domain.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: October 18, 2005
    Assignee: LSI Logic Corporation
    Inventors: Hung Nguyen, Keith Dang