Patents by Inventor Keith Downes

Keith Downes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070262416
    Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.
    Type: Application
    Filed: May 10, 2006
    Publication date: November 15, 2007
    Applicant: International Business Machines Corporation
    Inventors: Ebenezer Eshun, Ronald Bolam, Douglas Coolbaugh, Keith Downes, Natalie Feilchenfeld, Zhong-Xiang He
  • Publication number: 20070194390
    Abstract: The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.
    Type: Application
    Filed: February 22, 2006
    Publication date: August 23, 2007
    Inventors: Anil Chinthakindi, Douglas Coolbaugh, Keith Downes, Ebenezer Eshun, John Florkey, Heidi Greer, Robert Rassel, Anthony Stamper, Kunal Vaed
  • Publication number: 20070190718
    Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.
    Type: Application
    Filed: January 19, 2006
    Publication date: August 16, 2007
    Inventors: Douglas Coolbaugh, Keith Downes, Peter Lindgren, Anthony Stamper
  • Publication number: 20070155164
    Abstract: A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.
    Type: Application
    Filed: March 16, 2007
    Publication date: July 5, 2007
    Inventors: Steven Barkyoumb, Jonathan Chapple-Sokol, Edward Cooney, Keith Downes, Thomas McDevitt, William Murphy
  • Publication number: 20070065966
    Abstract: Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
    Type: Application
    Filed: September 19, 2005
    Publication date: March 22, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anil Chinthakindi, Douglas Coolbaugh, Keith Downes, Ebenezer Eshun, Zhong-Xiang He, Robert Rassel, Anthony Stamper
  • Publication number: 20070057343
    Abstract: A Metal Insulator-Metal (MIM) capacitor is formed on a semiconductor substrate with a base comprising a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. An ancillary MIM capacitor plate is selected either a lower electrode formed on the STI region in the semiconductor substrate or a doped well formed in the top surface of the semiconductor substrate. A capacitor HiK dielectric layer is formed on or above the MIM capacitor lower plate. A second MIM capacitor plate is formed on the HiK dielectric layer above the MIM capacitor lower plate.
    Type: Application
    Filed: September 12, 2005
    Publication date: March 15, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anil Chinthakindi, Douglas Coolbaugh, Keith Downes, Ebenezer Eshun, Zhong-Xiang He, Robert Rassel, Anthony Stamper, Kunal Vaed
  • Publication number: 20050253265
    Abstract: A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.
    Type: Application
    Filed: May 13, 2004
    Publication date: November 17, 2005
    Applicant: International Business Machines Corporation
    Inventors: Steven Barkyoumb, Jonathan Chapple-Sokol, Edward Cooney, Keith Downes, Thomas McDevitt, William Murphy