Patents by Inventor Keith E. Barrett

Keith E. Barrett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7472248
    Abstract: Techniques are presented for automatically generating Serial Presence Detect (SPD) contents. Standards for specific values associated with SPD contents are electronically represented with SPD tokens and rules. When a memory module is identified, a string of needed SPD tokens are acquired for that memory module. The SPD tokens are searched for in the standards and specific SPD values are assembled for the memory module based on the defined rules. The resulting SPD values which are associated with the rules form the needed SPD contents for the memory module. The SPD contents are used to configure an Electrically Erasable Programmable Read-Only Memory (EEPROM) on a memory module.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: December 30, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Keith E Barrett
  • Patent number: 7152139
    Abstract: Techniques are presented for automatically generating Serial Presence Detect (SPD) contents. Standards for specific values associated with SPD contents are electronically represented with SPD tokens and rules. When a memory module is identified, a string of needed SPD tokens are acquired for that memory module. The SPD tokens are searched for in the standards and specific SPD values are assembled for the memory module based on the defined rules. The resulting SPD values which are associated with the rules form the needed SPD contents for the memory module. The SPD contents are used to configure an Electrically Erasable Programmable Read-Only Memory (EEPROM) on a memory module.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: December 19, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Keith E Barrett
  • Patent number: 6452807
    Abstract: An interposer for evaluating an electrical characteristic of a ball grid array package or of a semiconductor die thereof. The interposer includes electrically conductive vias positioned correspondingly to bond pads of the semiconductor die and to the electrical contacts or terminals of a carrier substrate of the ball grid array package. Test pads, or contact pads, are disposed proximate an outer periphery of the interposer. Each of the test pads is in electrical communication, preferably by means of electrical traces, with a corresponding electrically conductive via of the interposer. In use, the interposer is aligned with and disposed between the semiconductor die and the carrier substrate such that the test pads of the interposer are at least partially located outside of a periphery of the semiconductor die. Thus, the test pads are exposed around the ball grid array semiconductor die and are, therefore, accessible to electrical testing equipment.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: September 17, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Keith E. Barrett
  • Patent number: 6081429
    Abstract: An interposer for evaluating an electrical characteristic of a ball grid array package or of a semiconductor die thereof. The interposer includes electrically conductive vias positioned correspondingly to bond pads of the semiconductor die and to the electrical contacts or terminals of a carrier substrate of the ball grid array package. Test pads, or contact pads, are disposed proximate an outer periphery of the interposer. Each of the test pads is in electrical communication, preferably by means of electrical traces, with a corresponding electrically conductive via of the interposer. In use, the interposer is aligned with and disposed between the semiconductor die and the carrier substrate such that the test pads of the interposer are at least partially located outside of a periphery of the semiconductor die. Thus, the test pads are exposed around the ball grid array semiconductor die and are, therefore, accessible to electrical testing equipment.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: June 27, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Keith E. Barrett