Abstract: Under the control of a processor executing a program, the timing margin of an electronic system can be improved by a series of operations that set the relative phase of receive and distributed clock signals from a number of given values, a relative phase of transmit and distributed clock signals from a number of given values, instruct an integrated circuit (IC) die to drive a sequence of outgoing data symbols and receive a sequence of incoming data symbols at those relative phase settings, and compares the outgoing symbols to the incoming symbols. A result of the comparison is recorded. The operations are repeated for other combinations of the discrete transmit and receive phase values. The relative phases are then set to a pair of values taken from the discrete transmit and receive phase values, which are closest to yielding a balanced timing margin as determined from the results of the comparisons.

Abstract: A method and apparatus for decreasing resonance in a printed circuit board (PCB) uses cuts in a ground plane to slow a signal passing through the ground plane. Cuts in the ground plane may be used alone or in conjunction with the lengthening of signal traces.

Abstract: A method for decreasing resonance in a printed circuit board (PCB) uses cuts in a ground plane to slow a signal passing through the ground plane. Cuts in the ground plane may be used alone or in conjunction with the lengthening of signal traces. Slowing the signal passing through the ground plane enables a mismatch between the signal transit time of the ground plane and a signal oscillation period of the circuit board to be obtained. The mismatch results in decreased resonance.

Abstract: An embodiment of the invention includes an apparatus that has a first clock on a memory controller hub that is set to a first clock receive time and a second clock on the memory controller hub set to a first clock transmit time. A first data is sent from the memory to the memory controller hub. A second data is sent from the memory to the memory controller hub wherein the second data is checked. At least one of the first clock and the second clock has at least one of a second clock receive time and a second clock transmit time adjusted.

Abstract: An embodiment of the invention includes an apparatus that has a first clock on a memory controller hub that is set to a first clock receive time and a second clock on the memory controller hub set to a first clock transmit time. A first data is sent from the memory to the memory controller hub. A second data is sent from the memory to the memory controller hub wherein the second data is checked. At least one of the first clock and the second clock has at least one of a second clock receive time and a second clock transmit time adjusted.

Abstract: Under the control of a processor executing a program, the timing margin of an electronic system can be improved by a series of operations that set the relative phase of receive and distributed clock signals from a number of given values, a relative phase of transmit and distributed clock signals from a number of given values, instruct an integrated circuit (IC) die to drive a sequence of outgoing data symbols and receive a sequence of incoming data symbols at those relative phase settings, and compares the outgoing symbols to the incoming symbols. A result of the comparison is recorded. The operations are repeated for other combinations of the discrete transmit and receive phase values. The relative phases are then set to a pair of values taken from the discrete transmit and receive phase values, which are closest to yielding a balanced timing margin as determined from the results of the comparisons.

Abstract: An apparatus for reducing signal degradation, propagation delay, and electromagnetic emission problems inherent in transmission of electrical signals along interconnect lines (such as lines which connect transistors in integrated circuits). The apparatus includes one or more pairs of generally parallel interconnect lines. Each line in each pair comprises line sections, and an inverter is connected between each pair of adjacent sections of each line. The inverters are arranged in staggered fashion, in the sense that the inverters connected along each line of a line pair are offset longitudinally from the inverters connected along the other line of the pair. Both bidirectional and unidirectional buses (groups of generally parallel interconnect line pairs) can be implemented in accordance with the invention.