Patents by Inventor Keith E. Downes
Keith E. Downes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9171778Abstract: A method and a semiconductor device are provided. The semiconductor device includes a partial via etched in a stacked structure and a trough above the partial via. The method includes performing thick wiring using selective etching while etching the partial via to an etch stop layer.Type: GrantFiled: January 28, 2014Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Douglas D. Coolbaugh, Keith E. Downes, Peter J. Lindgren, Anthony K. Stamper
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Patent number: 8753950Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.Type: GrantFiled: March 28, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Keith E. Downes, Peter J. Lindgren, Anthony K. Stamper
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Publication number: 20140151899Abstract: A method and a semiconductor device are provided. The semiconductor device includes a partial via etched in a stacked structure and a trough above the partial via. The method includes performing thick wiring using selective etching while etching the partial via to an etch stop layer.Type: ApplicationFiled: January 28, 2014Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas D. COOLBAUGH, Keith E. DOWNES, Peter J. LINDGREN, Anthony K. STAMPER
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Patent number: 8435864Abstract: A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.Type: GrantFiled: March 28, 2012Date of Patent: May 7, 2013Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Keith E. Downes, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Anthony K. Stamper
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Patent number: 8236663Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.Type: GrantFiled: September 22, 2009Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Keith E. Downes, Peter J Lindgren, Anthony K. Stamper
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Publication number: 20120190164Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.Type: ApplicationFiled: March 28, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas D. COOLBAUGH, Keith E. DOWNES, Peter J. LINDGREN, Anthony K. STAMPER
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Patent number: 8227849Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.Type: GrantFiled: February 17, 2010Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Ebenezer E Eshun, Ronald J Bolam, Douglas D Coolbaugh, Keith E Downes, Natalie B Feilchenfeld, Zhong-Xiang He
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Publication number: 20120184081Abstract: A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.Type: ApplicationFiled: March 28, 2012Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anil K. CHINTHAKINDI, Douglas D. COOLBAUGH, Keith E. DOWNES, Ebenezer E. ESHUN, Zhong-Xiang HE, Robert M. RASSEL, Anthony K. STAMPER
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Patent number: 8207568Abstract: Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.Type: GrantFiled: September 19, 2005Date of Patent: June 26, 2012Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Keith E. Downes, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Anthony K. Stamper
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Publication number: 20110108919Abstract: The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.Type: ApplicationFiled: January 13, 2011Publication date: May 12, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Keith E. Downes, Ebenezer E. Eshun, John E. Florkey, Heidi L. Greer, Robert M. Rassel, Anthony K. Stamper, Kunal Vaed
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Patent number: 7910450Abstract: The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.Type: GrantFiled: February 22, 2006Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Keith E. Downes, Ebenezer E. Eshun, John E. Florkey, Heidi L. Greer, Robert M. Rassel, Anthony K. Stamper, Kunal Vaed
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Patent number: 7879716Abstract: A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.Type: GrantFiled: March 16, 2007Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Steven P. Barkyoumb, Jonathan D. Chapple-Sokol, Edward C. Cooney, III, Keith E. Downes, Thomas L. McDevitt, William J. Murphy
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Publication number: 20100149723Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.Type: ApplicationFiled: February 17, 2010Publication date: June 17, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: EBENEZER E. ESHUN, RONALD J. BOLAM, DOUGLAS D. COOLBAUGH, KEITH E. DOWNES, NATALIE B. FEILCHENFELD, ZHONG-XIANG HE
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Patent number: 7728372Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.Type: GrantFiled: May 10, 2006Date of Patent: June 1, 2010Assignee: International Business Machines CorporationInventors: Ebenezer E. Eshun, Ronald J. Bolam, Douglas D. Coolbaugh, Keith E. Downes, Natalie B. Feilchenfeld, Zhong-Xiang He
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Publication number: 20100009509Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.Type: ApplicationFiled: September 22, 2009Publication date: January 14, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas D. Coolbaugh, Keith E. Downes, Peter J. Lindgren, Anthony K. Stamper
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Patent number: 7602068Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.Type: GrantFiled: January 19, 2006Date of Patent: October 13, 2009Assignee: International Machines CorporationInventors: Douglas D. Coolbaugh, Keith E. Downes, Peter J. Lindgren, Anthony K. Stamper
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Patent number: 7235487Abstract: A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.Type: GrantFiled: May 13, 2004Date of Patent: June 26, 2007Assignee: International Business Machines CorporationInventors: Steven P Barkyoumb, Jonathan D. Chapple-Sokol, Edward C. Cooney, III, Keith E. Downes, Thomas L. McDevitt, William J. Murphy