Abstract: One example includes a circuit. The circuit includes a first transistor having a first control terminal, a first current terminal, and a second current terminal. The first control terminal can be a first input to the circuit. The circuit also includes a second transistor having a second control terminal, a first current terminal, and a second current terminal. The second control terminal can be a second input to the circuit. The circuit also includes an adaptive bias current source coupled to the second current terminal of the respective first and second transistors. The circuit further includes a voltage offset generator coupled in parallel with the second transistor.

Abstract: A resonance-based DC-DC converter for converting a DC input voltage to a first DC output voltage (VOUT1) on a output conductor (9) includes an inductor (L) having a first terminal connected to a source (2) of a DC input voltage (VIN) and a second terminal coupled to a first conductor (4) and a capacitor (CRES) having a first terminal coupled to the first conductor. A first switch (SW1) is coupled between the resonance conductor and the output conductor to conduct inductor current (IL) into the output conductor during a first phase (Phase1). A second switch (SW2) is coupled between a second terminal of the capacitor and the output conductor to conduct inductor current through the capacitor into the output conductor (9) during a second phase (Phase2).

Abstract: A resonance-based DC-DC converter for converting a DC input voltage to a first DC output voltage (VOUT1) on a output conductor (9) includes an inductor (L) having a first terminal connected to a source (2) of a DC input voltage (VIN) and a second terminal coupled to a first conductor (4) and a capacitor (CRES) having a first terminal coupled to the first conductor. A first switch (SW1) is coupled between the resonance conductor and the output conductor to conduct inductor current (IL) into the output conductor during a first phase (Phase1). A second switch (SW2) is coupled between a second terminal of the capacitor and the output conductor to conduct inductor current through the capacitor into the output conductor (9) during a second phase (Phase2).

Abstract: An LDO regulator (10) produces an output voltage (Vout) by applying the output voltage to a feedback input (6) of a differential input stage (10A) and applying an output (3) of the differential input stage to a gate of a first follower transistor (MP4) having a source coupled to an input (8) of a class AB output stage (10C) which generates the output voltage. Demanded load current is supplied by the output voltage during a dip in its value to a gate of a second follower transistor (MP5) having a gate coupled to the output of the input stage to decrease current in a current mirror (MN5,6) having an output coupled to a current source (I1) and a gate of an amplifying transistor (MN7). This causes the current source to rapidly turn on the amplifying transistor to cause it to rapidly turn on a cascode transistor (MN3), causing it to turn on a pass transistor (MP3) of the output stage.

Abstract: Variable gain circuitry includes a first input transistor (M1) having a source coupled to a first conductor (32), a gate coupled to a first input voltage (Vin+), and a drain coupled to a second conductor (30). An input of a first current mirror (M3,M4) is coupled to the second conductor to receive a current corresponding to the difference between the first input voltage and a second input voltage (Vin?). An output of the first current mirror is coupled to a source of current (M2). A first transistor (M5) has a gate coupled to a third conductor (31), a source coupled to a reference voltage (VSS), and a drain coupled to conduct output current (Iout). A second transistor (M6) and a resistive element (M7) are coupled in series between the third conductor and the first reference voltage (VSS), a gate of the second transistor being coupled to the third conductor to produce a nonlinear relationship between currents of the first transistor and the second transistor.

Abstract: An LDO regulator (10) produces an output voltage (Vout) by applying the output voltage to a feedback input (6) of a differential input stage (10A) and applying an output (3) of the differential input stage to a gate of a first follower transistor (MP4) having a source coupled to an input (8) of a class AB output stage (10C) which generates the output voltage. Demanded load current is supplied by the output voltage during a dip in its value to a gate of a second follower transistor (MP5) having a gate coupled to the output of the input stage to decrease current in a current mirror (MN5,6) having an output coupled to a current source (I1) and a gate of an amplifying transistor (MN7). This causes the current source to rapidly turn on the amplifying transistor to cause it to rapidly turn on a cascode transistor (MN3), causing it to turn on a pass transistor (MP3) of the output stage.

Abstract: Variable gain circuitry includes a first input transistor (M1) having a source coupled to a first conductor (32), a gate coupled to a first input voltage (Vin+), and a drain coupled to a second conductor (30). An input of a first current mirror (M3,M4) is coupled to the second conductor to receive a current corresponding to the difference between the first input voltage and a second input voltage (Vin?). An output of the first current mirror is coupled to a source of current (M2). A first transistor (M5) has a gate coupled to a third conductor (31), a source coupled to a reference voltage (VSS), and a drain coupled to conduct output current (Iout). A second transistor (M6) and a resistive element (M7) are coupled in series between the third conductor and the first reference voltage (VSS), a gate of the second transistor being coupled to the third conductor to produce a nonlinear relationship between currents of the first transistor and the second transistor.

Abstract: An LDO regulator (10) produces an output voltage (Vout) by applying the output voltage to a feedback input (6) of a differential input stage (10A) and applying an output (3) of the differential input stage to a gate of a first follower transistor (MP4) having a source coupled to an input (8) of a class AB output stage (10C) which generates the output voltage. Demanded load current is supplied by the output voltage during a dip in its value to a gate of a second follower transistor (MP5) having a gate coupled to the output of the input stage to decrease current in a current mirror (MN5,6) having an output coupled to a current source (I1) and a gate of an amplifying transistor (MN7). This causes the current source to rapidly turn on the amplifying transistor to cause it to rapidly turn on a cascode transistor (MN3), causing it to turn on a pass transistor (MP3) of the output stage.

Abstract: An LDO regulator (10) produces an output voltage (Vout) by applying the output voltage to a feedback input (6) of a differential input stage (10A) and applying an output (3) of the differential input stage to a gate of a first follower transistor (MP4) having a source coupled to an input (8) of a class AB output stage (10C) which generates the output voltage. Demanded load current is supplied by the output voltage during a dip in its value to a gate of a second follower transistor (MP5) having a gate coupled to the output of the input stage to decrease current in a current mirror (MN5,6) having an output coupled to a current source (I1) and a gate of an amplifying transistor (MN7). This causes the current source to rapidly turn on the amplifying transistor to cause it to rapidly turn on a cascode transistor (MN3), causing it to turn on a pass transistor (MP3) of the output stage.

Abstract: Electrostatic discharge (ESD) protection structures utilizing bipolar conduction are disclosed. The structures each include a parasitic p-n-p bipolar transistor (102); some of the disclosed embodiments include this transistor within a silicon-controlled-rectifier (SCR) type of ESD protection structure. A p+ doped region (116, 216, 316, 416, 516) is disposed at a surface of an n-well (112, 212, 312, 412, 512) overlying a location (115, 215, 315, 415, 515) that receives both the n-well (112, 212, 312, 412, 512) implants and also the p-well (213, 313, 413, 513) implants. Preferably, the well implants are designed to provide retrograde doping profiles. The number of net impurities is reduced, and thus the base Gummel number is lowered, at the compensated well portion (112?, 212?, 312?, 412?, 512?), resulting in improved gain for the vertical bipolar device.

Abstract: A output driver architecture (100) is proposed that uses thin gate-oxide core and thin gate-oxide Drain-extended transistors that can directly interface with voltage supplies up to six times the normal rating of the transistor. A bias generator (101), level shifter (103) and output stage (105) are adapted to buffer an input signal with a voltage swing of less than the normal operating voltage of the transistors to an output signal with a voltage swing of up to approximately six times the normal operating voltage of the transistors. The bias generator is interfaced directly with a high voltage power supply and generates a bias voltage with a magnitude of less than the dielectric breakdown of the transistors internal to the level shifter and output stage.

Abstract: A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed.

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract: Electrostatic discharge (ESD) protection structures utilizing bipolar conduction are disclosed. The structures each include a parasitic p-n-p bipolar transistor (102); some of the disclosed embodiments include this transistor within a silicon-controlled-rectifier (SCR) type of ESD protection structure. A p+ doped region (116, 216, 316, 416, 516) is disposed at a surface of an n-well (112, 212, 312, 412, 512) overlying a location (115, 215, 315, 415, 515) that receives both the n-well (112, 212, 312, 412, 512) implants and also the p-well (213, 313, 413, 513) implants. Preferably, the well implants are designed to provide retrograde doping profiles. The number of net impurities is reduced, and thus the base Gummel number is lowered, at the compensated well portion (112′, 212′, 312′, 412′, 512′), resulting in improved gain for the vertical bipolar device.

Abstract: A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed.

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract: Electrostatic discharge (ESD) protection structures utilizing bipolar conduction are disclosed. The structures each include a parasitic p-n-p bipolar transistor (102); some of the disclosed embodiments include this transistor within a silicon-controlled-rectifier (SCR) type of ESD protection structure. A p+ doped region (116, 216, 316, 416, 516) is disposed at a surface of an n-well (112, 212, 312, 412, 512) overlying a location (115, 215, 315, 415, 515) that receives both the n-well (112, 212, 312, 412, 512) implants and also the p-well (213, 313, 413, 513) implants. Preferably, the well implants are designed to provide retrograde doping profiles. The number of net impurities is reduced, and thus the base Gummel number is lowered, at the compensated well portion (112′, 212′, 312′, 412′, 512′), resulting in improved gain for the vertical bipolar device.

Abstract: A output driver architecture (100) is proposed that uses thin gate-oxide core and thin gate-oxide Drain-extended transistors that can directly interface with voltage supplies up to six times the normal rating of the transistor. A bias generator (101), level shifter (103) and output stage (105) are adapted to buffer an input signal with a voltage swing of less than the normal operating voltage of the transistors to an output signal with a voltage swing of up to approximately six times the normal operating voltage of the transistors. The bias generator is interfaced directly with a high voltage power supply and generates a bias voltage with a magnitude of less than the dielectric breakdown of the transistors internal to the level shifter and output stage.

Abstract: A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed.

Abstract: Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad connection. The interface circuits employ high voltage tolerant, extended drain devices in circuit arrangements which insure that the stress of a failsafe event is only exhibited by the extended drain devices. A failsafe event is defined as a bond pad voltage which exceeds the supply voltage of the integrated circuit plus the threshold voltage of the transistors within the integrated circuit. Both failsafe output driver circuit and failsafe receiver circuit embodiments are provided.