Patents by Inventor Keith E. Winters

Keith E. Winters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatuses and methods for providing data from multiple memories
    Patent number: 9043578
    Abstract: Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Yi Chen, Yihua Zhang, Keith E. Winters
  • APPARATUSES AND METHODS FOR PROVIDING DATA FROM MULTIPLE MEMORIES
    Publication number: 20140258676
    Abstract: Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times.
    Type: Application
    Filed: May 20, 2014
    Publication date: September 11, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Yi Chen, Yihua Zhang, Keith E. Winters
  • Apparatuses and methods for providing data from multiple memories
    Patent number: 8732433
    Abstract: Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories are configured to provide data to the data bus responsive, at least in part, to a first address. The plurality of memories are further configured to provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may be configured to provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories configured to provide N bits of data to the data bus at different times.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Yi Chen, Yihua Zhang, Keith E. Winters
  • APPARATUSES AND METHODS FOR PROVIDING DATA FROM MULTIPLE MEMORIES
    Publication number: 20130054937
    Abstract: Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories are configured to provide data to the data bus responsive, at least in part, to a first address. The plurality of memories are further configured to provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may be configured to provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories configured to provide N bits of data to the data bus at different times.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Yi Chen, Yihua Zhang, Keith E. Winters