Abstract: A split-gate EEPROM transistor includes a channel region (22) formed in a vertically disposed semiconductor body (58) and residing intermediate to a drain region (26) and a source region (24). A select gate electrode (28) is horizontally disposed on a semiconductor substrate (20). A floating gate electrode (30) resides adjacent to the channel region (22) and overlies the select gate electrode (28). A control gate electrode (32) resides adjacent to the control gate electrode (30) and also overlies the select gate electrode (28). In operation, the select gate electrode (28) regulates the flow of electrical charge from the source region (24) into the channel region (22), and provides a field plate electrical isolation for adjacent memory cells in an EEPROM array.

Abstract: A method for forming a capped shallow trench isolation (CaSTI) structure begin by etching a trench opening (210). The opening (210) is filled with an oxide or like trench fill material (216b) via a deposition and chemical mechanical polish (CMP) step. The plug (216b) is reactive ion etched (RIE) to recess a top of the plug (216b) into the trench opening (210) to form a recessed plug region (216c). A silicon nitride or oxynitride capping layer (218b) is then formed over the recessed plug region (216c) via another deposition and polishing step. The nitride cap layer (218b) protects the underlying region (216c) from erosion due to active area preparation, cleaning, and processing.

Abstract: A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Abstract: A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.

Abstract: A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.

Abstract: A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Abstract: A method for forming a random access memory cell within four separate trench regions (106, 108, 110, and 112). One half of the memory cell has a first N-type transistor, which is a latch transistor (500), has a current electrode (101), a current electrode (126), and a gate electrode (114). A second N-type transistor, which is a word-line select transistor (504), has a first current electrode (101), a second current electrode (128), and a gate electrode (116). A P-channel pull up transistor (502) has a first current electrode (103), a second current electrode (124), and a gate electrode (114). The coupling of the electrodes (101 and 103) form a storage node of the one half of the memory cell which is contacted electrically by a conductive contact (140).

Abstract: A semiconductor dielectric (10) is formed by providing a base layer (12) having a surface. A thin interface layer (13) is formed at the surface of the base layer (12). The thin interface layer has a substantial concentration of both nitrogen and fluorine. A thermal oxide layer (14) is formed overlying the interface layer (13). A deposited dielectric layer (16) is formed overlying the thermal oxide layer (14). The deposited dielectric layer (16) is optionally densified by a thermal heat cycle. The deposited dielectric layer (16) has micropores that are misaligned to micropores in the thermal oxide layer (14) to provide enhanced features which the nitrogen/fluorine interface further improves the dielectric's features.

Abstract: A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Abstract: A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.

Abstract: A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the conductive layer (18) sidewall functions as a gate dielectric for the transistor (10). A conductive region is formed within the opening. The conductive region has a first current electrode region (28) and a second control electrode region (34) and a channel region (30) laterally adjacent the sidewall dielectric layer (22). A plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates, and/or CMOS NAND, NOR, and inverter gates with one or more inputs.

Abstract: A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34).

Abstract: An integrated circuit (10) has a vertical device, such as a transistor (71), formed by epitaxial growth from a substrate (12) and a horizontal device, such as a transistor (73, 75) grown epitaxially from the vertical device. In accordance with one embodiment of the invention, all six transistors of an SRAM cell can be formed in single crystal material for improved device characteristics and increased cell density. Utilization of various combinations of vertical and horizontal devices permits a large degree of vertical integration within semiconductor devices.

Abstract: A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.

Abstract: A method for forming an air region or an air bridge overlying a base layer (12). Air regions (20a, 20b, 28a, and 48) are formed overlying the base layer (12) to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form many other microstructures or microdevices. The air regions (20a, 20b, 28a, and 48) are formed by either selectively removing a sacrificial spacer (16a and 16b) or by selectively removing a sacrificial layer (28, 40). The air regions (20a, 20b, 28a, and 48) are sealed, enclosed, or isolated by either a selective growth process or by a non-conformal deposition technique. The air regions (20a, 20b, 28a, and 48) may be formed under any pressure, gas concentration, or processing condition (i.e. temperature, etc.). The air regions (20a, 20b, 28a, and 48) may be formed at any level within an integrated circuit.

Abstract: A fax system is automated herein by using a modem (10), a computer (12), and an office network which coupled the computer (12) to a plurality of end-user computers (26). A fax is received by the computer (12) through the modem (10). Once the fax is received by the computer (12), a program (14) stores the fax in a computer file (15) in a non-text format. Code (18) converts the non-text format of file (15) to a text format (17) which is read by a pattern recognition program (18). The program (18) determines, from the file (17), a destination of the fax document. The destination can be one or more of a printer (24), a computer in the plurality of computers (26), a default computer, or a default storage location (e.g., disk storage). A log file (19) is kept by computer (12) to record the operations of the computer (12) and receipt and routing information regarding received faxes. The control code (22) coordinates the other programs in memory (13).

Abstract: A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34). A capacitor (69) is formed overlying and coupled to the vertical transistor (10) in order to form a dynamic random access memory (DRAM) cell.

Abstract: A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34).

Abstract: A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each formed via one of either selective growth, epitaxial growth, in-situ doping, and/or ion implantation. A gate electrode or control electrode (34) is formed laterally adjacent the channel region (28). A selective/epitaxial growth step is used to connect the conductive layer (16) to the control electrode (34) and forms a control electrode interconnect which is reliable and free from electrical short circuits to the current electrodes (26 and 30). The transistor (10) may be vertically stacked to form compact inverter circuits.

Abstract: A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.