Patents by Inventor Keith E. Ypma
Keith E. Ypma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10600667Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.Type: GrantFiled: May 23, 2019Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch
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Publication number: 20190279892Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.Type: ApplicationFiled: May 23, 2019Publication date: September 12, 2019Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch
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Patent number: 10347519Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the water based on the comparison.Type: GrantFiled: January 15, 2019Date of Patent: July 9, 2019Assignee: Micron Technology, Inc.Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch
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Publication number: 20190148202Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.Type: ApplicationFiled: January 15, 2019Publication date: May 16, 2019Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch
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Patent number: 10242901Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.Type: GrantFiled: July 26, 2018Date of Patent: March 26, 2019Assignee: Micron Technology, Inc.Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch
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Publication number: 20180330976Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.Type: ApplicationFiled: July 26, 2018Publication date: November 15, 2018Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch
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Patent number: 10062595Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.Type: GrantFiled: July 24, 2017Date of Patent: August 28, 2018Assignee: Micron Technology, Inc.Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch
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Publication number: 20170352563Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.Type: ApplicationFiled: July 24, 2017Publication date: December 7, 2017Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch
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Publication number: 20170256501Abstract: A method of determining a lateral misregistration between levels of a semiconductor structure comprises imaging at least one first alignment mark in a first level of the structure and at least one second alignment mark in a second level of the structure. A digital image of the first and second alignment marks is formed, each of which are defined by a set of points having an x-value and a y-value. The x-values and y-values of points defining the first alignment mark and points defining the second alignment mark are averaged to determine a center of the first alignment mark and a center of the second alignment mark. An x-coordinate and a y-coordinate of the center of the first alignment mark is subtracted from the respective x-coordinate and y-coordinate of the center of the second alignment mark to determine a lateral misregistration between the first level and the second level.Type: ApplicationFiled: March 7, 2016Publication date: September 7, 2017Inventors: Yang Chao, Joseph L. Hess, Keith E. Ypma, Kurt J. Bossart
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Patent number: 9754895Abstract: A method of determining a lateral misregistration between levels of a semiconductor structure comprises imaging at least one first alignment mark in a first level of the structure and at least one second alignment mark in a second level of the structure. A digital image of the first and second alignment marks is formed, each of which are defined by a set of points having an x-value and a y-value. The x-values and y-values of points defining the first alignment mark and points defining the second alignment mark are averaged to determine a center of the first alignment mark and a center of the second alignment mark. An x-coordinate and a y-coordinate of the center of the first alignment mark is subtracted from the respective x-coordinate and y-coordinate of the center of the second alignment mark to determine a lateral misregistration between the first level and the second level.Type: GrantFiled: March 7, 2016Date of Patent: September 5, 2017Assignee: Micron Technology, Inc.Inventors: Yang Chao, Joseph L. Hess, Keith E. Ypma, Kurt J. Bossart
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Patent number: 9748128Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.Type: GrantFiled: June 1, 2016Date of Patent: August 29, 2017Assignee: Micron Technology, Inc.Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch