Abstract: According to one aspect of the present invention, an apparatus is provided in which a first switching device is used to connect a first node to a second node and disconnect the first node from the second node based upon the value of a first control signal. The first node is continuously connected to a first voltage source. The first switching device is capable of withstanding continuous application of the first voltage source. A second switching device is used to connect the second node to a third node when the first node is disconnected from the second node and to disconnect the second node from the third node when the first node is connected to the second node.

Abstract: According to one aspect of the present invention, an apparatus is provided in which a first switching device is used to connect a first node to a second node and disconnect the first node from the second node based upon the value of a first control signal. The first node is continuously connected to a first voltage source. The first switching device is capable of withstanding continuous application of the first voltage source. A second switching device is used to connect the second node to a third node when the first node is disconnected from the second node and to disconnect the second node from the third node when the first node is connected to the second node.

Abstract: According to one aspect of the present invention, an apparatus is provided in which a first switching device is used to connect a first node to a second node and disconnect the first node from the second node based upon the value of a first control signal. The first node is continuously connected to a first voltage source. The first switching device is capable of withstanding continuous application of the first voltage source. A second switching device is used to connect the second node to a third node when the first node is disconnected from the second node and to disconnect the second node from the third node when the first node is connected to the second node.

Abstract: According to one aspect of the present invention, an apparatus is provided in which a first switching device is used to connect a first node to a second node and disconnect the first node from the second node based upon the value of a first control signal. The first node is continuously connected to a first voltage source. The first switching device is capable of withstanding continuous application of the first voltage source. A second switching device is used to connect the second node to a third node when the first node is disconnected from the second node and to disconnect the second node from the third node when the first node is connected to the second node.

Abstract: A processor which includes at least a pair of call stacks and a pair of register files which may be utilized for running processes. The processor includes circuitry for detecting when an interrupt has occurred and switching from a stack and registers being utilized by a running process to a clean stack and registers to be utilized by the interrupting process. The processor then runs an interrupt start process which places the process interrupted and the circuitry utilized by that process into a condition in which the process may be safely interrupted. Similarly, the process circuitry detects when the interrupt is completed, performs a context switch in which the original stack and register are again made available, and switches to a process adapted to place the interrupted routine in an appropriate state to restart.

Abstract: A flash memory system includes a user interface and array controller. The user interface receives the user command issued by the processor and has the ability to queue a plurality of commands for execution. The user interface further functions as an arbiter to control the priority of commands to be executed. The array controller performs the operations on the flash array such as program and erase. The array controller consists of a general purpose processor with program memory which is programmable by the user. The program memory stores one or more algorithms that can be executed by the array controller. The algorithm is selected according to the command received at the user interface. The algorithms can be customized simply by programming the program memory. The system further provides an interrupt mechanism which enables the flash memory system to perform a context switch of a higher priority command with the lower priority, but currently executing, command.