Abstract: The invention provides testing of a chemically-sensitive transistor device, such as an ISFET device, without exposing the device to liquids. In one embodiment, the invention performs a first test to calculate a resistance of the transistor. Based on the resistance, the invention performs a second test to transition the testing transistor among a plurality of modes. Based on corresponding measurements, a floating gate voltage is then calculated with little or no circuitry overhead. In another embodiment, the parasitic capacitance of at least either the source or drain is used to bias the floating gate of an ISFET. A driving voltage and biasing current are applied to exploit the parasitic capacitance to test the functionality of the transistor.

Abstract: The invention provides testing of a chemically-sensitive transistor device, such as an ISFET device, without exposing the device to liquids. In one embodiment, the invention performs a first test to calculate a resistance of the transistor. Based on the resistance, the invention performs a second test to transition the testing transistor among a plurality of modes. Based on corresponding measurements, a floating gate voltage is then calculated with little or no circuitry overhead. In another embodiment, the parasitic capacitance of at least either the source or drain is used to bias the floating gate of an ISFET. A driving voltage and biasing current are applied to exploit the parasitic capacitance to test the functionality of the transistor.

Abstract: An ion-sensitive circuit can include a charge accumulation device, to accumulate a plurality of charge packets as a function of an ion concentration of a fluid, and at least one control and readout transistor, to generate an output signal as a function of the accumulated plurality of charge packets, the output signal representing the ion concentration of the solution. The charge accumulation device can include a first charge control electrode above a first electrode semiconductor region, an electrically floating gate structure above a gate semiconductor region and below an ion-sensitive passivation surface, a second charge control electrode above a second electrode semiconductor region, and a drain diffusion region. The first control electrode can control entry of charge into a gate semiconductor region in response to a first control signal. The ion-sensitive passivation surface can be configured to receive the fluid.

Abstract: A semiconductor device, comprising a first field effect transistor (FET) connected in series to a second FET, and a third FET connected in series to the first FET and the second FET. The semiconductor device further includes bias circuitry coupled to the first FET and the second FET, and an output conductor coupled to a terminal of the second FET, wherein the output conductor obtains an output signal from the second FET that is independent of the first FET.

Abstract: The invention provides testing of a chemically-sensitive transistor device, such as an ISFET device, without exposing the device to liquids. In one embodiment, the invention performs a first test to calculate a resistance of the transistor. Based on the resistance, the invention performs a second test to transition the testing transistor among a plurality of modes. Based on corresponding measurements, a floating gate voltage is then calculated with little or no circuitry overhead. In another embodiment, the parasitic capacitance of at least either the source or drain is used to bias the floating gate of an ISFET. A driving voltage and biasing current are applied to exploit the parasitic capacitance to test the functionality of the transistor.

Abstract: An ion-sensitive circuit can include a charge accumulation device, to accumulate a plurality of charge packets as a function of an ion concentration of a fluid, and at least one control and readout transistor, to generate an output signal as a function of the accumulated plurality of charge packets, the output signal representing the ion concentration of the solution. The charge accumulation device can include a first charge control electrode above a first electrode semiconductor region, an electrically floating gate structure above a gate semiconductor region and below an ion-sensitive passivation surface, a second charge control electrode above a second electrode semiconductor region, and a drain diffusion region. The first control electrode can control entry of charge into a gate semiconductor region in response to a first control signal. The ion-sensitive passivation surface can be configured to receive the fluid.

Abstract: The described embodiments may provide a chemical detection circuit. The chemical detection circuit may comprise a column of chemically-sensitive pixels. Each chemically-sensitive pixel may comprise a chemically-sensitive transistor, and a row selection device. The chemical detection circuit may further comprise a column interface circuit coupled to the column of chemically-sensitive pixels and an analog-to-digital converter (ADC) coupled to the column interface circuit. Each column interface circuit and column-level ADC may be arrayed with other identical circuits and share critical resources such as biasing and voltage references, thereby saving area and power.

Abstract: In one implementation, a chemical sensor is described. The chemical sensor includes chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A dielectric material defines an opening extending to the upper surface of the floating gate conductor. A conductive sidewall spacer is on a sidewall of the opening and contacts the upper surface of the floating gate conductor.

Abstract: An ion-sensitive circuit can include a charge accumulation device, to accumulate a plurality of charge packets as a function of an ion concentration of a fluid, and at least one control and readout transistor, to generate an output signal as a function of the accumulated plurality of charge packets, the output signal representing the ion concentration of the solution. The charge accumulation device can include a first charge control electrode above a first electrode semiconductor region, an electrically floating gate structure above a gate semiconductor region and below an ion-sensitive passivation surface, a second charge control electrode above a second electrode semiconductor region, and a drain diffusion region. The first control electrode can control entry of charge into a gate semiconductor region in response to a first control signal. The ion-sensitive passivation surface can be configured to receive the fluid.

Abstract: In one implementation, a chemical sensor is described. The chemical sensor includes a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A dielectric material defines an opening extending to the upper surface of the floating gate conductor. A conductive element on a sidewall of the opening and extending over an upper surface of the dielectric material.

Abstract: In one implementation, a chemical sensor is described. The chemical sensor includes a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A dielectric material defines an opening extending to the upper surface of the floating gate conductor. A conductive element is on a sidewall of the opening and spaced away from an upper surface of the dielectric material, the conductive element communicating with the floating gate conductor.

Abstract: A method of fabricating a microwell in an array structure is disclosed herein. The array structure can include a plurality of field effect transistors (FETs), where each FET has a gate structure. The method can include disposing a titanium nitride (TiN) layer on at least one conductive layer coupled to the gate structure of at least one FET. A insulation layer can also be disposed on the array structure, where the insulation layer lies above the TiN layer. Further, an opening above the gate structure of the at least one FET can be etched to remove the insulation layer above the gate structure and to expose the TiN layer. A microwell with at least one sidewall formed from the insulation layer and with a bottom surface formed from the TiN layer is a result of the etching process.

Abstract: An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples.

Abstract: A floating electrode is used to detect ions in close proximity to the electrode. The electrode is charge coupled to other electrodes and to other transistors to form a pixel that can be placed into an array for addressable readout. It is possible to obtain gain by accumulating charge into another electrode or onto a floating diffusion (FD) node or directly onto the column line. It is desirable to achieve both a reduction in pixel size as well as increase in signal level. To reduce pixel size, ancillary transistors may be eliminated and a charge storage node with certain activation and deactivation sequences may be used.

Abstract: An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples.

Abstract: A chemically sensitive sensor with a lightly doped region that affects an overlap capacitance between a gate and an electrode of the chemical sensitive sensor. The lightly doped region extends beneath and adjacent to a gate region of the chemical sensitive sensor. Modifying the gain of the chemically sensitive sensor is achieved by manipulating the lightly doped region under the electrodes.

Abstract: To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Configurable pixels can be created to allow both common source read out as well as source follower read out. A plurality of the 1T pixels may form an array, having a number of rows and a number of columns and a column readout circuit in each column. A cascoded device enabled during readout may be used to provide increased programmable gain.

Abstract: A method of fabricating a microwell in an array structure is disclosed herein. The array structure can include a plurality of field effect transistors (FETs), where each FET has a gate structure. The method can include disposing a titanium nitride (TiN) layer on at least one conductive layer coupled to the gate structure of at least one FET. A insulation layer can also be disposed on the array structure, where the insulation layer lies above the TiN layer. Further, an opening above the gate structure of the at least one FET can be etched to remove the insulation layer above the gate structure and to expose the TiN layer. A microwell with at least one sidewall formed from the insulation layer and with a bottom surface formed from the TiN layer is a result of the etching process.

Abstract: The described embodiments may provide a chemical detection circuit. The chemical detection circuit may comprise a pixel array, a pair of analog-to-digital converter (ADC) circuit blocks, a pair of input/output (I/O) circuit blocks coupled to the pair of ADC circuit blocks respectively, and a plurality of serial link terminals coupled to the pair of IO circuit blocks. The pixel array may comprise a plurality of chemically-sensitive pixels formed in columns and rows. Each chemically-sensitive pixel may comprise: a chemically-sensitive transistor, and a row selection device.

Abstract: To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Configurable pixels can be created to allow both common source read out as well as source follower read out. A plurality of the 1T pixels may form an array, having a number of rows and a number of columns and a column readout circuit in each column. A cascoded device enabled during readout may be used to provide increased programmable gain.