Abstract: An image sensor IC may have a non-volatile memory for several functions. The functions may include storing control parameters for a camera autofocus module, part tracking data, and data for defect correction or color science. The non-volatile memory can in particular be an antifuse non-volatile memory, which may not need special light shielding.

Abstract: An analog to digital converter with increased sub-range resolution. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a full-range ADC having a first quantization accuracy configured to sample the analog communication signal across the full-range and a central sub-range ADC having a second quantization accuracy greater than the first quantization accuracy and configured to sample the analog communication signal across a central sub-range of the full-range. The ADC also includes signal combining circuitry configured to process outputs of the full-range ADC and the central sub-range ADC to create the digital communication signal.

Abstract: An analog to digital converter with increased sub-range resolution. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a plurality of sub-range ADCs, each sub-range ADC measuring the analog communication signal across at least one respective sub-range of the full-range, the plurality of sub-ranges extending across the full-range, a central sub-range ADC having greater quantization accuracy than at least one other sub-range ADC. The ADC also includes signal combining circuitry operable to process outputs of the plurality of sub-range ADCs to create the digital communication signal.

Abstract: An analog to digital converter with increased sub-range resolution and method for using the analog to digital converter is described herein. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a plurality of sub-range ADCs, each sub-range ADC measuring the analog communication signal across at least one respective sub-range of the full-range, the plurality of sub-ranges extending across the full-range, a central sub-range ADC having greater quantization accuracy than at least one other sub-range ADC. The ADC also includes signal combining circuitry operable to process outputs of the plurality of sub-range ADCs to create the digital communication signal.

Abstract: An analog to digital converter with increased sub-range resolution and method for using the analog to digital converter is described herein. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a plurality of sub-range ADCs, each sub-range ADC measuring the analog communication signal across at least one respective sub-range of the full-range, the plurality of sub-ranges extending across the full-range, a central sub-range ADC having greater quantization accuracy than at least one other sub-range ADC. The ADC also includes signal combining circuitry operable to process outputs of the plurality of sub-range ADCs to create the digital communication signal.

Abstract: A Power Line Communications (PLC) device includes a processing module, memory, and a communication interface. In a first operation, the PLC device determines that the PLC device will service communications with a first remote PLC device according to a first PLC communication standard and configures the communication interface to service communications according to the first PLC communication standard. In a second operation, the PLC device determines that the PLC device will service communications with a second remote PLC device according to a second PLC communication standard and configures the communication interface to service communications according to the second PLC communication standard, wherein the first PLC communication standard and the second PLC communication standard are differing and incompatible PLC communication standards. The PLC device may also configure the communication interface to service non-PLC communications such as LAN, WAN, WLAN, cable modem, and other communications.

Abstract: A Power Line Communications (PLC) device includes a processing module, memory, a first PLC interface, and a second PLC interface. The PLC device determines that the PLC device will service communications with a first remote PLC device according to a first PLC communication standard and configures the first PLC interface to service communications to support the first PLC communication standard. The PLC device also determines that the PLC device will service communications with a second remote PLC device according to a second PLC communication standard and configures the second PLC interface to service communications to support the second PLC communication standard. The PLC device may service communications via the first and second PLC devices concurrently when the first and second PLC communication standards are not conflicting. The PLC device may transmit communications via the first PLC interface and receive ACKs via the second PLC interface.

Abstract: An image sensor array of active pixel elements is arranged in rows and columns. Each column has an output circuit for reading out pixel image signals. The output circuit includes a pair of sample capacitors, a switching circuit operable based upon pixel switches for applying pixel voltages to the pair of sample capacitors. At least one optically masked pixel is provided so that output image signals obtained therefrom represent substantially only the column fixed pattern noise (FPN). An image processing circuit records the column FPN for each column from the optically masked pixels, records the image signal from the sensor array of active pixels, and subtracts the column FPN column-wise from the image signal.

Abstract: A digital camera for capturing and processing images of different resolutions and a corresponding method for down-scaling a digital image are provided. The method includes forming an image of a real scene on an image sensor that is made up of a plurality of pixels arranged in a matrix. The method further includes addressing and reading pixels in the matrix to obtain analog quantities related to the pixels luminance values, converting the analog quantities from the pixels matrix into digital values, and processing the digital values to obtain a data file representing the image of the real scene. To reduce computation time and power consumption, the addressing and reading of the pixels includes selecting a group of pixels from the matrix, and storing the analog quantities related to the pixels of the selected group of pixels into an analog storing circuit. The stored analog quantities are averaged to obtain an analog quantity corresponding to an average pixel luminance value.

Abstract: A method for manufacturing an image sensor including an array of pixels and an imaging lens exit pupil for focusing rays of light onto the array of pixels is provided. Each pixel includes a light sensitive region and at least one optical element associated therewith. The method includes positioning the at least one optical element for each pixel relative to its associated light sensitive region based upon a range of acceptable angles of incidence for the rays of light from the imaging lens exit pupil.

Abstract: A method for manufacturing an image sensor including an array of pixels and an imaging lens exit pupil for focusing rays of light onto the array of pixels is provided. Each pixel includes a light sensitive region and at least one optical element associated therewith. The method includes positioning the at least one optical element for each pixel relative to its associated light sensitive region based upon a range of acceptable angles of incidence for the rays of light from the imaging lens exit pupil.

Abstract: An image sensor array of active pixel elements is arranged in rows and columns. Each column has an output circuit for reading out pixel image signals. The output circuit includes a pair of sample capacitors, a switching circuit operable based upon pixel switches for applying pixel voltages to the pair of sample capacitors. At least one optically masked pixel is provided so that output image signals obtained therefrom represent substantially only the column fixed pattern noise (FPN). An image processing circuit records the column FPN for each column from the optically masked pixels, records the image signal from the sensor array of active pixels, and subtracts the column FPN column-wise from the image signal.

Abstract: A solid state image sensor may include a pixel array of an active pixel type including three transistors and a photodiode for each pixel. Pixel reset values may be read out one row at a time and stored in a frame store. Pixel signal values may also be read out a row at a time. The stored reset values may be subtracted, for example, by a read/write/modify circuit to remove kTC noise. The readout of the reset and signal values may be interleaved, and the offset between read and reset for each row may be selected to control frame exposure.

Abstract: A digital camera for capturing and processing images of different resolutions and a corresponding method for down-scaling a digital image are provided. The method includes forming an image of a real scene on an image sensor that is made up of a plurality of pixels arranged in a matrix. The method further includes addressing and reading pixels in the matrix to obtain analog quantities related to the pixels luminance values, converting the analog quantities from the pixels matrix into digital values, and processing the digital values to obtain a data file representing the image of the real scene. To reduce computation time and power consumption, the addressing and reading of the pixels includes selecting a group of pixels from the matrix, and storing the analog quantities related to the pixels of the selected group of pixels into an analog storing circuit. The stored analog quantities are averaged to obtain an analog quantity corresponding to an average pixel luminance value.

Abstract: A method of processing digital images in devices for acquiring both individual images and image sequences, comprising the step of acquiring images in color filter array (CFA) format and the step of reducing the resolution of the images acquired. In order to reduce computing time and energy consumption, the resolution-reduction step processes the images directly in CFA format.