Abstract: High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 ? or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.

Abstract: A probe or an electrical connector comprises a substrate with a surface having a plurality of electrical contact locations. A shaped elongated electrical conductor has a first end coupled to one of the electrical contact locations and a second end thereof which projects away from the electrical contact location and through an aperture in a sheet of material. The sheet is disposed to be spaced apart from the surface of the substrate. At the second end of the elongated electrical conductor there is a tip structure, which is larger than the aperture in the sheet of material. The tip structure has a pointed portion thereof. The tip structure is disposed against contact locations of a contact surface.

Abstract: A method of fabricating a high-quality relaxed SiGe-on-insulator substrate material is provided in which a prefabricated silicon-on-insulator substrate is first exposed to an unstrained Ge-containing source and then heated (annealed/oxidized) to cause Ge diffusion and thermal mixing of Ge within a single-crystal Si-containing layer of the prefabricated silicon-on-insulator substrate. The unstrained Ge-containing source can comprise a solid Ge-containing source, a gaseous Ge-containing source, or ions of Ge.

Abstract: A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 ? thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge.

Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

Abstract: A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed. The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided.

Abstract: An interposer having one or more hollow electrical contact buttons disposed in a carrier. The interposer is formed by disposing sacrificial posts in vias of the carrier. The electrical contact buttons are formed on the sacrificial posts by a metallizing process in desired pattern using a mask. The sacrificial posts are made of a material that thermally decomposes upon application of heat without altering the carrier or the electrical contact buttons.

Abstract: Methods for fabricating Land Grid Array (LGA) interposer contacts that are both conducting and elastic. Also provided are LGA interposer contacts as produced by the inventive methods. Provided is LGA type which utilizes a pure unfilled elastomer button core that is covered with an electrically-conductive material that is continuous from the top surface to the bottom surface of the button structure. In order to obviate the disadvantages and drawbacks which are presently encountered in the technology pertaining to the fabrication and structure of land grid arrays using electrically-conductive interposer contacts, there is provided both methods and structure for molding elastomer buttons into premetallized LGA carrier sheets, and wherein the non-conductive elastomer buttons are surface-metallized in order to convert them into conductive electrical contacts.

Abstract: A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 ?) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

Abstract: A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Abstract: A method of forming a high-quality relaxed SiGe alloy layer on a bulk Si-containing substrate is provided. The method of the present invention includes growing a strained SiGe alloy layer on a Si-containing substrate that has a porous Si-containing layer at or near the surface of the Si-containing substrate. The porous layer is formed by an electrolytic anodization process. The pores create free volume below the strained SiGe layer which can serve to accommodate strain relaxation during SiGe deposition or a subsequent heating step. The subsequent heating step is optional and is performed to further increase the relaxation of the SiGe alloy layer. The buried porous structure allows for a unique relaxation mechanism compared to prior art methods.

Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.

Abstract: Probes for electronic devices are described. The probe is formed by ball bonding a plurality of wires to contact locations on a fan out substrate surface. The wires are cut off leaving stubs. A patterned polymer sheet having electrical conductor patterns therein is disposed over the stubs which extend through holes in the sheet. The ends of the wires are flattened to remit the polymer sheet in place. The wire is connected to an electrical conductor on the polymer sheet which is converted to a contact pad on the polymer sheet. A second wire is ball bonded to the pad on the polymer sheet and cut to leave a second stub. The polymer sheet is laser cut so that each second stub is free to move independently of the other second studs. The ends of the second stubs are disposed against contact locations of an electronic device, such as an FC chip, to test the electronic device.

Abstract: A SIMOX (separation by implanted oxygen) process is provided that forms a silicon-on-insulator (SOI) substrate having a buried oxide with improved electrical properties. The process implements at least one of the following processing steps into SIMOX: (I) lowering of the oxygen ion dose in the base oxygen ion implant step; (II) off-setting the implant energy of the room temperature (RT) implant step to a value that is about 5 to about 20% lower than the base ion implant step; and (III) creating a soak cycle, i.e., pre-annealing step, prior to the internal oxidation anneal which allows dissolution of Si and SiOx precipitates in the oxygen implanted region. The temperature and time of the soak cycle as well as the base implant dose are critical in determining the final BOX quality.

Abstract: A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implanted-ion rich region in the Si-containing substrate. The implanted-ion rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

Abstract: A method of forming a relaxed SiGe-on-insulator substrate having enhanced relaxation, significantly lower defect density and improved surface quality is provided. The method includes forming a SiGe alloy layer on a surface of a first single crystal Si layer. The first single crystal Si layer has an interface with an underlying barrier layer that is resistant to Ge diffusion. Next, ions that are capable of forming defects that allow mechanical decoupling at or near said interface are implanted into the structure and thereafter the structure including the implanted ions is subjected to a heating step which permits interdiffusion of Ge throughout the first single crystal Si layer and the SiGe layer to form a substantially relaxed, single crystal and homogeneous SiGe layer atop the barrier layer. SiGe-on-insulator substrates having the improved properties as well as heterostructures containing the same are also provided.

Abstract: An interposer having one or more hollow electrical contact buttons disposed in a carrier. The interposer is formed by disposing sacrificial posts in vias of the carrier. The electrical contact buttons are formed on the sacrificial posts by a metallizing process in desired pattern using a mask. The sacrificial posts are made of a material that thermally decomposes upon application of heat without altering the carrier or the electrical contact buttons.

Abstract: A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implant rich region in the Si-containing substrate. The implant rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

Abstract: Methods for forming a patterned SOI region in a Si-containing substrate is provided which has geometries of about 0.25 ?m or less. Specifically, one method includes the steps of: forming a patterned dielectric mask on a surface of a Si-containing substrate, wherein the patterned dielectric mask includes vertical edges that define boundaries for at least one opening which exposes a portion of the Si-containing substrate; implanting oxygen ions through the at least one opening removing the mask and forming a Si layer on at least the exposed surfaces of the Si-containing substrate; and annealing at a temperature of about 1250° C. or above and in an oxidizing ambient so as to form at least one discrete buried oxide region in the Si-containing substrate. In one embodiment, the mask is not removed until after the annealing step; and in another embodiment, the Si-containing layer is formed after annealing and mask removal.