Patents by Inventor Keith G. Bartlett

Keith G. Bartlett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4681430
    Abstract: An improved method for automatically focusing an integrated circuit manufacturing projection step and repeat photolithography printer employing an optical signal to focus the printer is disclosed. The automatic focusing is achieved by reflecting an optical signal off a photoresist layer on the surface of a wafer and converting the reflected optical signal into an electronic signal employed to focus the printer. According to the preferred embodiment of the present invention, a dye which absorbs light at the wavelength the optical signal is added to the photoresist layer to improve the quality of the reflected optical signal thereby considerably reducing or eliminating focusing errors.
    Type: Grant
    Filed: August 27, 1986
    Date of Patent: July 21, 1987
    Assignee: Hewlett-Packard Company
    Inventors: Atul Goel, Keith G. Bartlett, W. R. Trutna
  • Patent number: 4508591
    Abstract: An etching solution for the dissolution of silicon dioxide through a portable conformable mask, with PMMA as the etch stop layer, has been developed which eliminates resist lifting and non-uniform lateral etching, thereby providing the improved oxide edge definitions required for 1 micron line geometries in VLSI chips.
    Type: Grant
    Filed: March 8, 1984
    Date of Patent: April 2, 1985
    Assignee: Hewlett-Packard Company
    Inventors: Keith G. Bartlett, Mary A. Caolo
  • Patent number: 4362809
    Abstract: An improved photoetch technique is presented of the portable-conformable-mask type wherein a thin top layer of resist and a thick planarizing layer are deposited on a substrate and the thin layer is exposed and developed to produce a portable-conformable-mask. The improvement involves dissolving a suitable dye in a layer between the thin top layer and the substrate. The dye is preferably selected to absorb light of the wavelengths used to expose the top layer but does not interfere with processing of the other layers.
    Type: Grant
    Filed: March 30, 1981
    Date of Patent: December 7, 1982
    Assignee: Hewlett-Packard Company
    Inventors: Mung Chen, William R. Trutna, Jr., Michael P. C. Watts, Keith G. Bartlett, Gary Hillis
  • Patent number: 4247915
    Abstract: A semiconductor memory of the static type employs a pair of cross-coupled driver transistors and a pair of access transistors along with load devices which are punch-through elements resembling short channel MOS transistors without gates. The punch-through elements each have an electrode integral with the drain of one of the driver transistors, and another electrode coupled to a voltage supply. A cell layout of very small size is possible.
    Type: Grant
    Filed: January 2, 1979
    Date of Patent: January 27, 1981
    Assignee: Texas Instruments Incorporated
    Inventor: Keith G. Bartlett
  • Patent number: 4246592
    Abstract: A semiconductor memory of the static type employs a pair of cross-coupled driver transistors which are formed by a method which results in field oxide over the source and drain regions of the MOS transistors. Access transistors are formed by a different method and have silicon gates self-aligned with their source and drain diffusions. The load devices are punch-through elements resembling short channel transistors without gates. These features permit a cell layout with a minimum of space used for the cross-coupling connections, and the polysilicon address line can cross over the ground line, producing a very small cell size.
    Type: Grant
    Filed: January 2, 1979
    Date of Patent: January 20, 1981
    Assignee: Texas Instruments Incorporated
    Inventor: Keith G. Bartlett
  • Patent number: 4246593
    Abstract: A semiconductor memory of the static type employs a pair of cross-coupled driver transistors which are formed by a method which results in field oxide over the source and drain regions. Access transistors are formed by a different method and have silicon gates self-aligned with their source and drain diffusions. The load devices are ion-implanted polycrystalline silicon strips which overlie the driver transistors. These features permit a very small cell layout with a minimum of space used for the cross-coupling connections, and the polysilicon address line can cross over the ground line.
    Type: Grant
    Filed: January 2, 1979
    Date of Patent: January 20, 1981
    Assignee: Texas Instruments Incorporated
    Inventor: Keith G. Bartlett
  • Patent number: 4170492
    Abstract: A method of selectively enhancing the growth rate of silicon oxide in the manufacture of semiconductor devices results in a reduction in encroachment of oxide into the edges of areas masked by silicon nitride. Implanting an impurity material into the monocrystalline silicon surface, without annealling to correct implant damage, causes the surface to oxidize at lower temperatures and faster rates.
    Type: Grant
    Filed: April 18, 1978
    Date of Patent: October 9, 1979
    Assignee: Texas Instruments Incorporated
    Inventors: Keith G. Bartlett, Laurence R. Jordan, Randall S. Mundt