Patents by Inventor Keith G. Boyer

Keith G. Boyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8643974
    Abstract: Systems and methods that sense or obtain environmental conditions of a tape drive and dynamically apply voltage biases to tape head assembly elements based on the sensed/obtained environmental conditions to reduce tape stain accumulation and prolong tape head performance. Detection of different first and second sets of environmental conditions (e.g., in relation to temperatures, humidity levels, tape movement directions, etc.) may result in respective first and second voltage bias level sets being applied to respective first and second head assembly element sets. For instance, different first and second voltage bias level sets may be applied to the same head assembly elements (e.g., the first and second head assembly element sets may be the same), or the first and second voltage bias level sets may be applied to different head assembly elements (e.g., the first and second head assembly element sets may be at least partially different).
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: February 4, 2014
    Assignee: Oracle International Corporation
    Inventors: Charles C. Partee, Keith G. Boyer
  • Patent number: 8413014
    Abstract: A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: April 2, 2013
    Assignee: Oracle America, Inc.
    Inventors: Jin Lu, Keith G. Boyer
  • Patent number: 8006172
    Abstract: A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out (“FIFO”) memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and detects cycle slip. The iterative decoder thereafter performs a predetermined number of iterations to decode the data. Responsive to encoded data failing to converge after the predetermined number of iterations, the encoded data is communicated from the FIFO memory to an auxiliary decoder module. The auxiliary iterative error correction code decoder performs a second predetermined number of iterations to decode the data wherein the number of iterations performed by the auxiliary iterative error correction code decoder is greater than the primary iterative error correction code decoder.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: August 23, 2011
    Assignee: Oracle America, Inc.
    Inventors: Keith G. Boyer, Jin Lu, Mark Hennecken
  • Publication number: 20110029843
    Abstract: A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 3, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Jin Lu, Keith G. Boyer
  • Publication number: 20090019335
    Abstract: A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out (“FIFO”) memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and detects cycle slip. The iterative decoder thereafter performs a predetermined number of iterations to decode the data. Responsive to encoded data failing to converge after the predetermined number of iterations, the encoded data is communicated from the FIFO memory to an auxiliary decoder module. The auxiliary iterative error correction code decoder performs a second predetermined number of iterations to decode the data wherein the number of iterations performed by the auxiliary iterative error correction code decoder is greater than the primary iterative error correction code decoder.
    Type: Application
    Filed: July 10, 2007
    Publication date: January 15, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Keith G. Boyer, Jin Lu, Mark Hennecken
  • Patent number: 7409622
    Abstract: A system and method for Reverse Error Correction Coding. The system includes a Constraint encoder, an Error Correction Code encoder, and a uniform interleaver. The Constraint encoder receives a source data stream and generates a first intermediate encoded data stream satisfying a first predetermined timing data constraint. The Error Correction Code encoder receives the first intermediate encoded data stream and generates a second intermediate encoded data stream having one or more Error Correction Code based elements. The uniform interleaver receives the second intermediate encoded data stream and generates a channel data stream having the one or more Error Correction Code based elements and satisfying a second predetermined timing data constraint.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: August 5, 2008
    Assignee: Storage Technology Corporation
    Inventors: Jin Lu, Keith G. Boyer
  • Patent number: 6764006
    Abstract: An apparatus includes a tape read head bias signal control circuit configured to present to a tape read head a first amplitude bias signal in response to at least a first control signal and a second amplitude bias signal in response to at least a second control signal, wherein the second amplitude is lower than the first amplitude. The read head, thereby, may have a reduced operating temperature.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: July 20, 2004
    Assignee: Storage Technology Corporation
    Inventors: Robert G. Brocko, Keith G. Boyer, James C. Cates, Larry D. Blanchard
  • Patent number: 6347389
    Abstract: The pipelined high speed Reed-Solomon error/erasure decoder processes multiple code words in a pipelined fashion. The pipelined high speed Reed-Solomon error/erasure decoder is designed to process Reed-Solomon encoded words that have been corrupted in a digital system by processing errors as well as erasures through a simple iterative modified syndrome process. The iterative nature of this method provides for limited computational effort at each step of the pipeline. This allows the pipelined high speed Reed-Solomon error/erasure decoder to easily handle full or shortened Reed-Solomon codes, as well as parallel processing to achieve higher data rates. The iterative modified syndrome process is one of the pipelined steps. It relieves the erasure pre-shifting burden from the Berlekamp/Massey synthesis process, which reduces the number of cycles required at that stage of processing. The decoder proceeds classically with a Chien Search for any remaining error locations.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: February 12, 2002
    Assignee: Storage Technology Corporation
    Inventor: Keith G. Boyer
  • Patent number: 6311259
    Abstract: A system and method for allowing uni-directional data to be read in the reverse direction as well as the forward direction uses a data buffer to reverse the order of data read from storage media. Data are read from the storage media in the reverse direction and stored in a data buffer. Pointers are set up to track record boundaries of the data storedin the data buffer. The data are read from the data buffer in the opposite direction from which they are stored and sent to a host in the forward direction. Cyclic redundancy checks can be performed as data are read from the storage media in the reverse direction and read from the data buffer in the forward direction.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: October 30, 2001
    Assignee: Storage Technology Corporation
    Inventors: Keith G. Boyer, Richard A. Gill, Thomas H. Gohl
  • Patent number: 5533039
    Abstract: A fault tolerant protocol for determining the beginning of data despite the presence of burst errors in a frame of transmitted data. The fault tolerant protocol of the present invention provides in the frame of transmitted data a plurality of different preamble characters, P, in a prearranged order before the beginning of data. The frame of transmitted data before the plurality of preamble characters is a plurality of identical synchronization characters, S. The protocol of the present invention detects a predetermined number, n, of sequential synchronization characters in the plurality, s, of synchronization characters. Upon detection, a synchronization signal is issued indicating acquisition of synchronization. Upon receipt of the synchronization signal, the invention detects a majority, m, of preamble characters in the plurality of preamble characters. When a majority of the preamble characters have been detected, the beginning of data is determined.
    Type: Grant
    Filed: September 22, 1993
    Date of Patent: July 2, 1996
    Assignee: Storage Technology Corporation
    Inventor: Keith G. Boyer
  • Patent number: 5410546
    Abstract: The present invention discloses a method and apparatus for computing CRC codes for fixed length page buffers of user data where the user data arrives from a transmission device in variable length packets with the packet contents being out of sequential order. The received data is written to a storage device after being restored to the correct sequential order. The data packets are comprised of a header portion and a data portion. The transmission and compression methods commonly employed by the transmission device dictates that the header portion of each packet follows the data portion. The present invention computes a complete CRC code for the data stored in a page buffer in real time as the packets are received by using several registers for saving intermediate CRC codes and circuitry to combine partial CRC codes for those packet portions received out of order.
    Type: Grant
    Filed: November 1, 1993
    Date of Patent: April 25, 1995
    Assignee: Storage Technology Corporation
    Inventors: Keith G. Boyer, Kenneth R. Burns, Thomas H. Gohl, Terry R. Gottehrer, Bernie R. Marasco, Michael R. Stephens, Robert D. Thompson