Abstract: A semiconductor device (2) includes a semiconductor substrate (12) having a surface (13) formed with a first recessed region (20). A first dielectric material (60) is deposited in the first recessed region and formed with a second recessed region (76), and a second dielectric material (100) is grown over the first dielectric material to seal the second recessed region.

Abstract: A semiconductor device (2) includes a semiconductor substrate (12) having a surface (13) formed with a first recessed region (20). A first dielectric material (60) is deposited in the first recessed region and formed with a second recessed region (76), and a second dielectric material (100) is grown over the first dielectric material to seal the second recessed region.

Abstract: A sealable air gap (14) is formed between a heating element (16) and a base (11) to improve the thermal isolation of a semiconductor heater (10). A top layer (17) is formed over the heating element (16) which seals the air gap (14) so that the sealable air gap (14) can be at either atmospheric pressure or under a vacuum. The semiconductor heater (10) can be used in a variety of applications including as a heat source to adjust the resistivity of an overlying resistive layer (18). The embodiments of the semiconductor heater (10) also include a chemical sensor (20). Heat from a heating element (26) is used to keep an overlying layer of chemical sensing material (28) at an optimal temperature. The embodiments of the present invention also include a transducer (40) to heat a fluid (52) in a well (55) such as in an ink jet application.

Abstract: A trench power switching transistor (10) is fabricated having sub-micron features on a body layer (26) without using sub-micron lithography. An opening in a field oxide layer (28) defines an area for implanting a source region (30) in the body layer (26) that is self-aligned to a first edge (28A) and a second edge (28B) of the field oxide layer (28). Sidewall spacers (32) are formed in accordance with the first and second edges (28A and 28B) of the field oxide layer (28). A trench is aligned to the sidewall spacers (32) and formed centered within the source region (30). An implant layer (42) formed between sections of the power switching transistor (10) is aligned to the sidewall spacers (32) at the first and second edges (28A and 28B).

Abstract: The resistors of heater elements are formed by chemical vapor deposition of polycrystalline silicon at at least one of a flat temperature profile of 620.degree. C. and a ramped temperature profile of 620.degree. C. to 640.degree. C. in a first embodiment. Such method of forming the polysilicon result in a predominantly uniform grain size of approximately 1000 .ANG., where grain size can vary between 200 .ANG. to 1000 .ANG.. Alternatively, the resistors are formed by chemical vapor deposition of amorphous polysilicon at at least one of a flat temperature profile at a temperature below 580.degree. C. and a ramped temperature profile of 565.degree. C. to 575.degree. C. In the alternative embodiment, the polysilicon has a grain size of at least 1000 .ANG.. During the ion implantation of either p-type or n-type dopants into the polysilicon, a flood gun located in an ion implanter emits low energy electrons to neutralize the build-up of positive charges on the polysilicon surface.