Abstract: Systems and methods are disclosed for reducing reset noise in an image sensor. Voltage on the column read out is sensed during reset. When the voltage reaches a desired threshold level, a voltage is asserted on the column read out line that turns off the reset transistor. Using column circuitry to turn off the reset transistor may be used to reduce noise associated with the reset switch. In example embodiments, a comparator may be included on each column line to determine when the threshold voltage has been reached and to trigger the assertion of the turn off voltage on the column line.

Abstract: Systems and methods are disclosed for reducing reset noise in an image sensor. Voltage on the column read out is sensed during reset. When the voltage reaches a desired threshold level, a voltage is asserted on the column read out line that turns off the reset transistor. Using column circuitry to turn off the reset transistor may be used to reduce noise associated with the reset switch. In example embodiments, a comparator may be included on each column line to determine when the threshold voltage has been reached and to trigger the assertion of the turn off voltage on the column line.

Abstract: Systems and methods are disclosed for reducing reset noise in an image sensor. Voltage on the column read out is sensed during reset. When the voltage reaches a desired threshold level, a voltage is asserted on the column read out line that turns off the reset transistor. Using column circuitry to turn off the reset transistor may be used to reduce noise associated with the reset switch. In example embodiments, a comparator may be included on each column line to determine when the threshold voltage has been reached and to trigger the assertion of the turn off voltage on the column line.

Abstract: Systems and methods are disclosed for reducing reset noise in an image sensor. Voltage on the column read out is sensed during reset. When the voltage reaches a desired threshold level, a voltage is asserted on the column read out line that turns off the reset transistor. Using column circuitry to turn off the reset transistor may be used to reduce noise associated with the reset switch. In example embodiments, a comparator may be included on each column line to determine when the threshold voltage has been reached and to trigger the assertion of the turn off voltage on the column line.

Abstract: A system and method adaptively control sensitivity, on a pixel-by-pixel basis, of a digital imager. An illumination intensity level mapping controller determines a number of pixels of image data having illumination intensity levels within a first defined range of illumination intensity levels and determines an illumination intensity level mapping function based upon the determined number of pixels within the first defined range of illumination intensity levels. An exposure controller determines a number of pixels having illumination intensity levels within a second defined range of illumination intensity levels and determines an integration time based upon the determined number of pixels having illumination intensity levels within the second defined range of illumination intensity levels.

Abstract: A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

Abstract: A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

Abstract: A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

Abstract: A sense node voltage relating to light intensity incident upon a light-detecting element is measured. To realize this measurement, a first integration reset pulse is generated to enable a resetting of the sense node voltage to a voltage value substantially equal to a reset voltage value associated with the first integration reset pulse, an edge of the first integration reset pulse triggering a beginning of a first integration period. Thereafter, a second integration reset pulse is generated to enable a resetting of the sense node voltage to a voltage value substantially equal to a reset voltage value associated with the second integration reset pulse, an edge of the second integration reset pulse triggering a beginning of a second integration period.

Abstract: A low power imaging array has a plurality of pixels wherein each pixel converts an intensity of incident light into electrical energy. An operational transconductance amplifier is utilized in conjunction with the imaging array to process the image signals from the low power imaging array. The operational transconductance amplifier includes a current mirror stage with a current mirror gain factor. The current mirror gain factor is selected based on a pixel noise level introduced by the low power imaging array such that current mirror gain factor noise introduced by the current mirror gain factor results in an overall noise level that is less than or equal to a predetermined level.

Abstract: A method for determining a pixel output value of an imager; the imager having a plurality of pixels, a reset switch associated with each pixel and a select switch associated with each pixel; due to incident illumination upon a pixel of the imager after a reset period. The method captures a first pixel output value when the reset switch is OFF during a reset period and the select switch is ON during a reset period and captures a second pixel output value when the select switch is ON near an end of an integration period. If the second pixel output value is captured when the select switch is ON near an end of a first integration period, the first pixel output value may be captured when the reset switch is OFF during a reset period preceding the first integration period and the select switch is ON during a reset period preceding the first integration period.

Abstract: An area is imaged with a non-standard aspect ratio, e.g. wide aspect ratio, digital imager to produce pixels of image data. At least a portion of the produced pixels of image data corresponding to the captured non-standard aspect ratio image is displayed beginning, for a given frame of pixels of image data, at a column of pixels of image data corresponding to a predetermined column of imaged pixels. The number of columns of display pixels is different than the number of columns of imaged pixels. Motion is detected in the imaged pixels so that a motion responsive portion of the imaged pixels corresponding to the captured non-standard aspect ratio image corresponding to a window of the imaged pixels having motion detected therein can be displayed.

Abstract: A circuit and method measure the output voltage of a CMOS pixel in a manner that substantially reduces all columnar pattern noise due to mismatches in the signal processing circuits including the correlated double sampling amplifiers and A/D converters. The circuit includes a test switch, operatively connected between a reference voltage source and a correlated double sampling amplifier, for applying a test voltage from the reference voltage source when the state of the test switch is ON to the correlated double sampling amplifier.

Abstract: A pixel site of a semiconductor imager structure includes a substrate layer of a first dopant type; a photodiode being formed of a doped well region within the substrate layer, the doped well region being of a second dopant type; a transistor wherein a terminal of the transistor being provided within the doped well region, the terminal of the transistor being of the second dopant type and of a dopant concentration greater than a dopant concentration of the doped well region; and an oxide layer formed over the substrate layer, the doped well region, and the terminal of the transistor. The oxide layer has a varying height such that a height of the oxide layer associated with the doped well region is thicker than a height of the oxide layer associated with the terminal of the transistor. The oxide layer includes a step region being located where the height of the oxide layer transitions from the height associated with the doped well region to the height associated with the terminal of the transistor.

Abstract: A sense node voltage relating to light intensity incident upon a light-detecting element is measured. To realize this measurement, a first integration reset pulse is generated to enable a resetting of the sense node voltage to a voltage value substantially equal to a reset voltage value associated with the first integration reset pulse, an edge of the first integration reset pulse triggering a beginning of a first integration period. Thereafter, a second integration reset pulse is generated to enable a resetting of the sense node voltage to a voltage value substantially equal to a reset voltage value associated with the second integration reset pulse, an edge of the second integration reset pulse triggering a beginning of a second integration period.

Abstract: A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

Abstract: A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

Abstract: A method and system provide in-stream compression of bytes of digital image sensor data. A specified number of least significant bits of the byte of digital image sensor data is masked or dropped to reduce the amount of image data if a frame of image data. After masking, alternate bytes of digital image sensor data are subtracted to produce an entropy-reduced data model. The difference bytes of digital image sensor data are split into a predetermined number of channels, each channel having a bit width such that the sum of the bit widths of each channel equals a bit width of the byte of digital image sensor data. Each channel is operated upon by a distinct cumulative distribution function before being multiplexed. The multiplexed digital image sensor data is encoded by arithmetic compression encoding. The method and system also utilize a division-free method of arithmetic encoding to simplify the hardware requirements of encoding.

Abstract: A pixel site of a semiconductor imager structure includes a substrate layer of a first dopant type; a photodiode being formed of a doped well region within the substrate layer, the doped well region being of a second dopant type; a transistor wherein a terminal of the transistor being provided within the doped well region, the terminal of the transistor being of the second dopant type and of a dopant concentration greater than a dopant concentration of the doped well region; and an oxide layer formed over the substrate layer, the doped well region, and the terminal of the transistor. The oxide layer has a varying height such that a height of the oxide layer associated with the doped well region is thicker than a height of the oxide layer associated with the terminal of the transistor. The oxide layer includes a step region being located where the height of the oxide layer transitions from the height associated with the doped well region to the height associated with the terminal of the transistor.

Abstract: A compact digital camera including a control subsystem, which itself includes a microprocessor, and an imaging subsystem and a power management subsystem, each in communication with the control subsystem. The imaging subsystem includes a retractable and extendable lens holder including a lens mount adapted to hold a lens assembly, a camera body surface and a biasing component positioned between the lens mount and the camera body surface. The biasing component is configured to move the lens assembly from a stored position to an operating position. The power management subsystem includes power selection-isolation circuitry, battery charging circuitry in communication with the power selection-isolation circuitry and power arbitration circuitry.