Abstract: An apparatus for reading a bit of a memory array includes a bit cell column, voltage enhancement circuitry, and control circuitry. The voltage enhancement circuitry is configured to couple a bitline to a reference node. The control circuitry is configured to, in response to a read request for a bitcell element of a plurality of bitcell elements, couple a current source to the bitcell column such that a read current from the current source flows from the source line, through the bitcell column and the voltage enhancement circuitry, to the reference node and determine a state for the bitcell element based on a voltage between the source line and the reference node. The voltage enhancement circuitry is configured to generate, when the read current flows through the voltage enhancement circuitry, a voltage at the bitline that is greater than a voltage at the reference node.

Abstract: A method for storing data includes determining, using a first match line, that a match word satisfies a first content addressable memory (CAM) word stored in a CAM array, wherein the CAM array is configured to store a second CAM word that matches the first CAM word. The method further includes determining that a first parity bit associated with the first CAM word matches a first parity of the first CAM word. The method further includes, in response to determining that the first parity bit associated with the first CAM word matches the first parity determining, using the first match line, a first random access memory (RAM) word stored in a RAM array and outputting the first RAM word.

Abstract: An apparatus for reading a bit of a memory array includes a bit cell column, voltage enhancement circuitry, and control circuitry. The voltage enhancement circuitry is configured to couple a bitline to a reference node. The control circuitry is configured to, in response to a read request for a bitcell element of a plurality of bitcell elements, couple a current source to the bitcell column such that a read current from the current source flows from the source line, through the bitcell column and the voltage enhancement circuitry, to the reference node and determine a state for the bitcell element based on a voltage between the source line and the reference node. The voltage enhancement circuitry is configured to generate, when the read current flows through the voltage enhancement circuitry, a voltage at the bitline that is greater than a voltage at the reference node.

Abstract: A programmable impedance based memory device includes a programmable impedance element, read circuitry configured to determine a resistance of the programmable impedance element during a write operation; and, write circuitry configured to change the resistance of the programmable impedance element as part of performing the write operation, wherein the write circuitry is further configured to terminate the write operation based on the read circuitry detecting that the resistance of the programmable impedance element has passed a threshold value.

Abstract: A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in series so that if either one of the delays fails, a delay will still be maintained within the SRAM cell. The critical areas of the delays may be positioned so that a common line of sight cannot be made between each delay and a circuit node.

Abstract: This disclosure describes voting circuits where an output is generated based on a plurality of inputs. A first plurality of logic paths connects the output to a high voltage. Each logic path of the first plurality of logic paths includes two transistors. A second plurality of logic paths connects the output to the low voltage. Each logic path of the second plurality of logic paths comprises two transistors. Based on N or N?1 of the inputs agreeing, the output is driven to either the low voltage or the high voltage via a subset of logic paths of the first and second plurality of logic paths.

Abstract: This disclosure is directed to techniques for preventing or reducing perturbations of an output signal of a differential amplifier caused by ionizing radiation incident upon the amplifier. The amplifier may include an amplification module that includes a plurality of amplification units configured to amplify a difference between a first component and a second component of a differential voltage signal to generate a plurality of amplified difference signals each corresponding to the amplified difference. The amplifier may further include a combination module that combines the plurality of amplified difference signals to generate a common output signal corresponding to the amplified difference.

Abstract: This disclosure is directed to techniques for preventing or reducing perturbations of an output signal of a differential amplifier caused by ionizing radiation incident upon the amplifier. The amplifier may include an amplification module that includes a plurality of amplification units configured to amplify a difference between a first component and a second component of a differential voltage signal to generate a plurality of amplified difference signals each corresponding to the amplified difference. The amplifier may further include a combination module that combines the plurality of amplified difference signals to generate a common output signal corresponding to the amplified difference.

Abstract: This disclosure describes voting circuits where an output is generated based on a plurality of inputs. A first plurality of logic paths connects the output to a high voltage. Each logic path of the first plurality of logic paths includes two transistors. A second plurality of logic paths connects the output to the low voltage. Each logic path of the second plurality of logic paths comprises two transistors. Based on N or N?1 of the inputs agreeing, the output is driven to either the low voltage or the high voltage via a subset of logic paths of the first and second plurality of logic paths.

Abstract: The disclosure describes an antenna protection circuit for use in circuits where Single Event Transients from energetic particles is a concern. The antenna protection circuit may include at least three diodes, connected electrically in series and arranged such that at most all but one of the at least three diodes produce a transient current pulse from an energetic particle. During the transient current pulse event, the remaining diode remains reverse biased thereby sufficiently blocking the transient current pulse and an SET does not occur on the signal node. The antenna protection circuit may be constructed so that no unshorted parasitic p-n junction structure is associated with any of the diodes in the circuit, which would otherwise have to be explicitly included in the at least three diodes.

Abstract: A process flow for fabricating shallow trench isolation (STI) devices with direct body tie contacts is provided. The process flow follows steps similar to standard STI fabrication methods except that in one of the etching steps, body tie contacts are etched through the nitride layer and STI oxide layer, directly to the body tie. This process flow provides a direct body tie contact to mitigate floating body effects but also eliminates hysteresis and transient upset effects common in non-direct body tie contact configurations, without the critical alignment requirements and critical dimension control of the layout.

Abstract: The disclosure describes an antenna protection circuit for use in circuits where Single Event Transients from energetic particles is a concern. The antenna protection circuit may include at least three diodes, connected electrically in series and arranged such that at most all but one of the at least three diodes produce a transient current pulse from an energetic particle. During the transient current pulse event, the remaining diode remains reverse biased thereby sufficiently blocking the transient current pulse and an SET does not occur on the signal node. The antenna protection circuit may be constructed so that no unshorted parasitic p-n junction structure is associated with any of the diodes in the circuit, which would otherwise have to be explicitly included in the at least three diodes.

Abstract: A process flow for fabricating shallow trench isolation (STI) devices with direct body tie contacts is provided. The process flow follows steps similar to standard STI fabrication methods except that in one of the etching steps, body tie contacts are etched through the nitride layer and STI oxide layer, directly to the body tie. This process flow provides a direct body tie contact to mitigate floating body effects but also eliminates hysteresis and transient upset effects common in non-direct body tie contact configurations, without the critical alignment requirements and critical dimension control of the layout.

Abstract: Described herein is a majority carrier device. Specifically, an exemplary device may comprise source, channel, and drain regions in a thin semiconductor layer, and the source, channel, and drain region may all share a single doping type of varying concentrations. Further, the device may comprise an insulating layer above the channel region and a gate region above the insulating layer, such that the gate modulates the channel. The device described herein may eliminate the parasitic bipolar transistor and the sensitivity to excess minority carrier generation that results from single event effects (SEE) such as heavy ion hits.

Abstract: A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.

Abstract: A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.

Abstract: A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in series so that if either one of the delays fails, a delay will still be maintained within the SRAM cell. The critical areas of the delays may be positioned so that a common line of sight cannot be made between each delay and a circuit node.

Abstract: An antenna diode circuit is described. The antenna diode circuit includes two diodes connected in series between a signal line and ground. Alternatively, the antenna diode circuit is connected in series between a signal line and a power supply. In addition to protecting the signal line from charge accumulation during wafer fabrication, the antenna diode circuit prevents a single event transient glitch caused by a particle strike to either one of the diodes in the antenna diode circuit.

Abstract: A simulation model is used to predict a semiconductor device's response to a single event upset. The simulation model is connected to a model of the semiconductor device to be tested. The simulation model switches in an impedance path between a node to be tested in the semiconductor device model and an opposite voltage supply until a predefined amount of charge has been reached via sourcing (for a low to high voltage transition) or sinking (for a high to low voltage transition). When the predefined amount of charge has been reached, the impedance path is switched out. The switching of the impedance path approximates the charge movement that occurs from a heavy ion strike passing through a sensitive volume. By varying the predefined amount of charge, the semiconductor device's susceptibility to SEU can be predicted without having to resort to physical testing.

Abstract: A voltage divider circuit can be realized by dividing a higher than rated operating voltage across a plurality of MOS transistors. The voltage divider circuit can be used for a wide variety of ratios of low and high operating voltages. Only one gate input voltage is needed, minimizing power dissipation, heat, and hot carrier effects. The voltage divider circuit is employed in a voltage driver circuit to generate a high output voltage in response to a low voltage input while minimizing damage to the MOS transistors within the voltage driver circuit.