Abstract: Aspects of the present disclosure are directed to fabrication methods for analogue quantum systems (AQSs). Further aspects of the present disclosure are directed to methods for solving computational problems using an AQS. Methods for fabricating an AQS include generating a Hamiltonian based on a computational problem, which may be an optimization problem or a simulation problem. Further, the method includes identifying AQS fabrication parameters based on one or more identified measurement methods and the Hamiltonian. Lastly, an AQS can be fabricated based on the identified fabrication parameters. An AQS may be used inter alia to simulate a battery or interfaces.

Abstract: Quantum processing element and method to perform logic operations on a quantum processing element are disclosed. The quantum processing element includes: a semiconductor, a dielectric material forming an interface with the semiconductor, a plurality of dopant dots embedded in the semiconductor, each of the dopant dots comprising one or more dopant atoms and one or more electrons or holes confined within the dopant dots, wherein spin of an unpaired electron or hole of each dopant dot forms at least one qubit. The method includes the step of: controlling orientation of nuclear spins of the one or more dopant atoms in a pair of dopant dots and/or controlling a hyperfine interaction between nuclear spins of one or more dopant atoms and electron or hole spins of the unpaired electron or hole in the pair of dopant dots to perform a quantum logic operation on a corresponding pair of qubits.

Abstract: A quantum bit, quantum processing element, and one or more large-scale quantum processing systems are disclosed. the quantum bit includes: a first quantum dot embedded in the semiconductor substrate, the first quantum dot comprising a first donor atom cluster and a second quantum dot embedded in the semiconductor substrate, the second quantum dot comprising a second donor atom cluster. The first and second quantum dots share a single electron, and the quantum bit is electrically controlled utillising the hyperfine interaction between the single electron and one or more nuclear spins present in the first and second donor atom clusters.

Abstract: Aspects of the present disclosure involve systems, methods, devices, and the like for segmentation of the processor architecture platform. In one embodiment, a system and method are introduced which enable the use of a segmented platform in an extended network. The segmented platform is introduced for processing using standardized plugins enabling the use of processing and services available at the segmented network. In another embodiment, processing on the segmented platform can include the integration of microservices for the completion of the transaction.

Abstract: Aspects of the present disclosure are directed to quantum processing systems that include a plurality of donor atom qubits positioned in a semiconductor substrate. The system also comprises a plurality of control gates configured to control the donor atom qubits. The system further comprises an SLQD charge sensor fabricated on/in the semiconductor substrate. The SLQD charge sensor is configured to sense spin-states of two or more donor atom qubits, which are positioned within a sensing range of the SLQD charge sensor.

Abstract: A method for readout of a singlet-triplet qubit in a donor based quantum processing element is disclosed. The method includes: initialising the singlet-triplet qubit in a ground state |G; performing a shelving readout; using a final measured charge configuration of the singlet-triplet qubit to determine information about a current Zeeman energy difference; and using the information about the current Zeeman energy difference to adjust mapping of the shelving readout.

Abstract: A method for measuring the spin of an electron in a quantum dot that is tunnel coupled to a reservoir is disclosed. The method includes measuring a spin state of the injected electron while applying a ramped detuning for a time period.

Abstract: Aspects of the present disclosure involve systems, methods, devices, and the like for segmentation of the processor architecture platform. In one embodiment, a system and method are introduced which enable the use of a segmented platform in an extended network. The segmented platform is introduced for processing using standardized plugins enabling the use of processing and services available at the segmented network. In another embodiment, processing on the segmented platform can include the integration of microservices for the completion of the transaction.

Abstract: Aspects of the present disclosure involve systems, methods, devices, and the like for segmentation of the processor architecture platform. In one embodiment, a system and method are introduced which enable the use of a segmented platform in an extended network. The segmented platform is introduced for processing using standardized plugins enabling the use of processing and services available at the segmented network. In another embodiment, processing on the segmented platform can include the integration of microservices for the completion of the transaction.

Abstract: Aspects of the present disclosure involve systems, methods, devices, and the like for segmentation of the processor architecture platform. In one embodiment, a system and method are introduced which enable the use of a segmented platform in an extended network. The segmented platform is introduced for processing using standardized plugins enabling the use of processing and services available at the segmented network. In another embodiment, processing on the segmented platform can include the integration of microservices for the completion of the transaction.