Patents by Inventor Keith Grimes
Keith Grimes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7716543Abstract: A method and system for testing a modular data-processing component. Register information associated with a modular data-processing component to be tested at a test location can be identified and stored. The modular data-processing component can then be tested and removed from said test location. Thereafter, the register information can be retrieved and provided for use with testing of a new data-processing component at said test location without losing said register information during testing of multiple modular data-processing components. The register information can be, for example, PCI configuration data and the modular data-processing component can be an HAB.Type: GrantFiled: November 2, 2005Date of Patent: May 11, 2010Assignee: LSI CorporationInventors: Keith Grimes, Todd Jeffrey Egbert, Edmund Paul Fehrman
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Patent number: 7643958Abstract: An automated system for validating Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters has a computer, motherboard, a PCI-X bus and isolated test slot for operatively coupling a PCI/PCI adapter under test through the PCI-X bus to the motherboard. The isolated test slot is adapted and arranged to minimize degradation of data flow on the PCI-X bus such that a PCI-X adapter, mounted in the isolated test slot, can negotiate a required operating rate greater than PCI operating rates. It can be configured as a low profile slot in a low profile computer system, such as a 2U low profile system. A method for validating the PCI/PCI-X bus adapters includes operatively coupling the bus adapter under test to the motherboard, negotiating to the required operating rate and testing the functionality of the adapter. The operating rate of the bus adapter can be verified to ensure the PCI/PCI-X bus adapters are tested at required PCI/PC-X rates.Type: GrantFiled: December 4, 2007Date of Patent: January 5, 2010Assignee: LSI CorporationInventors: Keith Grimes, Todd Jeffrey Egbert, Edmund Paul Fehrman
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Patent number: 7389196Abstract: An automated system for validating Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters has a computer, motherboard, a PCI-X bus and isolated test slot for operatively coupling a PCI/PCI adapter under test through the PCI-X bus to the motherboard. The isolated test slot is adapted and arranged to minimize degradation of data flow on the PCI-X bus such that a PCI-X adapter, mounted in the isolated test slot, can negotiate a required operating rate greater than PCI operating rates. It can be configured as a low profile slot in a low profile computer system, such as a 2U low profile system. A method for validating the PCI/PCI-X bus adapters comprises operatively coupling the bus adapter under test to the motherboard, negotiating to the required operating rate and testing the functionality of the adapter. The operating rate of the bus adapter can be verified to ensure the PCI/PCI-X bus adapters are tested at required PCI/PC-X rates.Type: GrantFiled: October 31, 2005Date of Patent: June 17, 2008Assignee: LSI CorporationInventors: Keith Grimes, Todd Jeffrey Egbert, Edmund Paul Fehrman
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Publication number: 20080091980Abstract: An automated system for validating Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters has a computer, motherboard, a PCI-X bus and isolated test slot for operatively coupling a PCI/PCI adapter under test through the PCI-X bus to the motherboard. The isolated test slot is adapted and arranged to minimize degradation of data flow on the PCI-X bus such that a PCI-X adapter, mounted in the isolated test slot, can negotiate a required operating rate greater than PCI operating rates. It can be configured as a low profile slot in a low profile computer system, such as a 2U low profile system. A method for validating the PCI/PCI-X bus adapters comprises operatively coupling the bus adapter under test to the motherboard, negotiating to the required operating rate and testing the functionality of the adapter. The operating rate of the bus adapter can be verified to ensure the PCI/PCI-X bus adapters are tested at required PCI/PC-X rates.Type: ApplicationFiled: December 4, 2007Publication date: April 17, 2008Inventors: Keith Grimes, Tood Egbert, Edmund Fehrman
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Patent number: 7289925Abstract: Methods and systems assess timing of PCI signals. A test mode is initiated within a host adapter board. A clock signal is generated for the host adapter board. PCI signals are generated within the host adapter board. One or more PCI signal lines of the host adapter board are electronically selected; and timing (e.g., slew rate and/or clock-to-signal valid) of the one or more PCI signal lines is assessed.Type: GrantFiled: December 23, 2003Date of Patent: October 30, 2007Assignee: LSI CorporationInventors: Gordon Keith Grimes, William J. Schmitz, Gregory William Achilles
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Publication number: 20070100574Abstract: An automated system for validating Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters has a computer, motherboard, a PCI-X bus and isolated test slot for operatively coupling a PCI/PCI adapter under test through the PCI-X bus to the motherboard. The isolated test slot is adapted and arranged to minimize degradation of data flow on the PCI-X bus such that a PCI-X adapter, mounted in the isolated test slot, can negotiate a required operating rate greater than PCI operating rates. It can be configured as a low profile slot in a low profile computer system, such as a 2U low profile system. A method for validating the PCI/PCI-X bus adapters comprises operatively coupling the bus adapter under test to the motherboard, negotiating to the required operating rate and testing the functionality of the adapter. The operating rate of the bus adapter can be verified to ensure the PCI/PCI-X bus adapters are tested at required PCI/PC-X rates.Type: ApplicationFiled: October 31, 2005Publication date: May 3, 2007Inventors: Keith Grimes, Todd Egbert, Edmund Fehrman
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Publication number: 20070101200Abstract: A method and system for testing a modular data-processing component. Register information associated with a modular data-processing component to be tested at a test location can be identified and stored. The modular data-processing component can then be tested and removed from said test location. Thereafter, the register information can be retrieved and provided for use with testing of a new data-processing component at said test location without losing said register information during testing of multiple modular data-processing components. The register information can be, for example, PCI configuration data and the modular data-processing component can be an HAB.Type: ApplicationFiled: November 2, 2005Publication date: May 3, 2007Inventors: Keith Grimes, Todd Egbert, Edmund Fehrman
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Patent number: 7078924Abstract: A method for populating and depopulating components of negligible impedance facilitates the testing of circuit boards. The test circuitry may be formed upon the circuit board under test. Testing may be performed with great accuracy for the time between the triggering edge of a clock pulse and a resulting valid signal change. Slew rates of bus signals may be more easily measured.Type: GrantFiled: September 20, 2002Date of Patent: July 18, 2006Assignee: LSI Logic CorporationInventors: Keith Grimes, Raymond S. Rowhuff, William Schmitz
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Patent number: 6925588Abstract: Systems and methods for testing data lines to determine signal degradation in the data lines. A system includes a signal generator for generating a test pattern and for transferring the test pattern through the data lines. The system also includes an analyzer communicatively connected to the data lines to determine degradation of the test pattern in the data lines. The signal generator generates and transfers a first test pattern through the data lines. The first test pattern includes a first portion having a first polarity and a second portion having a second polarity. The signal generator then generates and transfers a second test pattern through the data lines in response to transferring the first test pattern. The test patterns may be repeated one or more times to determine cross talk caused by inductive coupling between data lines and additive reflections.Type: GrantFiled: December 23, 2002Date of Patent: August 2, 2005Assignee: LSI Logic CorporationInventors: G. Keith Grimes, Gregory W. Achilles
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Publication number: 20040123204Abstract: Systems and methods for testing data lines to determine signal degradation in the data lines. A system includes a signal generator for generating a test pattern and for transferring the test pattern through the data lines. The system also includes an analyzer communicatively connected to the data lines to determine degradation of the test pattern in the data lines. The signal generator generates and transfers a first test pattern through the data lines. The first test pattern includes a first portion having a first polarity and a second portion having a second polarity. The signal generator then generates and transfers a second test pattern through the data lines in response to transferring the first test pattern. The test patterns may be repeated one or more times to determine cross talk caused by inductive coupling between data lines and additive reflections.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Inventors: G. Keith Grimes, Gregory W. Achilles
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Publication number: 20040059975Abstract: A method for populating and depopulating components of negligible impedance facilitates the testing of circuit boards. The test circuitry may be formed upon the circuit board under test. Testing may be performed with great accuracy for the time between the triggering edge of a clock pulse and a resulting valid signal change. Slew rates of bus signals may be more easily measured.Type: ApplicationFiled: September 20, 2002Publication date: March 25, 2004Inventors: Keith Grimes, Raymond S. Rowhuff, William Schmitz