Abstract: A construction toy is disclosed which interconnects construction toys of different types. One version connects toys of the construction block type to toys of the hub and spoke type. Gripper posts (22) or gripper arms (34 and 46) on the interconnector create channels (24, 36 and 48, respectively) which receive a hub (40) from a hub and spoke construction toy. Spokes from the hub and spoke construction toy connect with the block toy at many different angles. Blocks from the block type construction toy connect normally on all faces of the base interconnector. Channels (24, 36 and 48) on the base allow variable hub (40) placement to accommodate the different sizes and spacings of the different toys. This invention maintains substantially all the possible connections of each toy after interconnection.

Abstract: A construction toy is disclosed which interconnects construction toys of different types. One version connects toys of the construction block type to toys of the hub and spoke type. Gripper posts (22) or gripper arms (34 and 46) on the interconnector create channels (24, 36 and 48, respectively) which receive a hub (40) from a hub and spoke construction toy. Spokes from the hub and spoke construction toy connect with the block toy at many different angles. Blocks from the block type construction toy connect normally on all faces of the base interconnector. Channels (24, 36 and 48) on the base allow variable hub (40) placement to accommodate the different sizes and spacings of the different toys. This invention maintains substantially all the possible connections of each toy after interconnection.

Abstract: A programmable logic device having a plurality of logic cells arranged in groups defining separate logic regions, both regional and multi-regional bus lines, and a crosspoint switch matrix which serves only to route signals from bus lines to inputs of the logic cells without logically combining two or more of the bus signals, i.e. without forming product terms. Rather, all logic is carried out by the logic cells themselves. In particular, the switch matrix is constructed so that each bus line can connect to one or more logic cell inputs, but each logic cell input can meaningfully connect to only one bus line without shorting. In one embodiment, each logic cell feeds one logic signal back to a regional bus line and can potentially feed back another logic signal through its region's universal select matrix to a universal bus line. The select matrix connects a subset of the region's potential feedback signals to the universal bus.

Abstract: A logic circuit which implements numerous logic functions, stored and combinational, without the use of flip-flops or different types of logic elements. This circuit provides a novel storage element which can emulate any logic function of its inputs. As shown in FIG. 8, a logic function generator (200) has at least three inputs. One input (218) responds to a control signal (202) and a second input (220) responds to a delayed function of the control signal (204). These two signals, in combination with the logic circuit output (210) and other input signals (206and 208), produce the output (210). The stored version of these signals can change on either the rising or falling edge (or both) of the controlling signal. Other combinational signals are also available at the output. The circuit's flexibility arises from the programming of the data bits in the logic function generator, either fixed at time of manufacture or by user programmable means.

Abstract: An integrated circuit package including a plurality of macrocells for connecting a logic circuit of the package to a plurality of external contacts of the package. At least one of the macrocells has an output driver that is enabled or disabled by a control signal for transmitting or preventing transmission of a logic signal to one of the contacts. The control signal is generated by a logic gate that receives and logically combines an individual output enable signal dedicated to that particular macrocell with a selected signal. One signal that may be selected is a regional output enable signal that is supplied to more than one macrocell. Each macrocell also has a feedback multiplexer selecting one signal to be sent to the logic circuit. Choices include a nonstored logic signal, a stored logic signal from a flip-flop register in the macrocell, a signal applied to the external contact associated with that macrocell, and a signal applied to another external contact associated with a different macrocell.

Abstract: A clock circuit having a logic gate with an output supplying a clock signal to a clock input of a storage element and with plural inputs, including an input connected to an external contact for receiving an external clock signal and an input connected to a logic circuit to receive a logic term, such as a product term or sum-of-products term. The logic gate logically combines the internally generated logic with the external clock signal to produce the clock signal for the storage element. The logic gate may be an AND, OR, NAND or NOR gate. A multiplexer with an output connected to an input of the logic gate and responsive to a control signal may select one of two or more logic terms, one of two or more external clock signals, or a fixed voltage signal.

Abstract: A programmable logic device having a programmable AND (product term) array formed with input terms on both global and local busses and with both global and local product term lines. Each macrocell of the device, whether as input/output macrocell connected to an I/O pin or a buried macrocell providing only feedback, connects to and receives an inputs both global and local product terms. In one embodiment, global product terms are connectable to the global bus and to a local bus corresponding to a particular group or quadrant of macrocells. Local product terms are only connectable to that local bus, and thus only a fraction of the terms available to the global product terms. In an alternate embodiment, global product terms are connectable to the global bus and to a set of local busses which is a prope subset of all of the local busses. Local product terms are connectable only to the particular local bus assigned to a particular group or quadrant of macrocells and to a fraction of the terms on the global bus.

Abstract: A programmable logic device having an AND array receiving inputs and having programmable product term lines output to an OR array, and an output macrocell associated with each of a plurality of input/output pins. Each macrocell has a plurality of sum term lines from the OR array which may selectively be combined or left distinct, and a plurality of flip-flop registers receiving input from the combined or distinct sum lines. Each flip-flop has product term programmable clock, reset and preset lines and a dedicated feedback line into the AND array. A selection circuit is provided for selecting combinatorial output from one or more sum term lines or registered output from one of the flip-flop registers. A product term programmable output enable selects either the output or disables the output buffer so that a pin may receive input signals fed through a dedicated line into the AND array.

Abstract: A nonvolatile memory cell employing a bistable RAM cell and an electrically erasable and electrically programmable (E.sup.2) floating gate memory device. The E.sup.2 cell is coupled between one of the input/output nodes of the RAM cell and a clear/recall line. The loads of the RAM cell are imbalanced, causing this cell to assume a predetermined state. If the E.sup.2 cell is in its erased state after a storage cycle, the potential on the store/recall line causes the RAM cell to assume its other stable state on recall.

Abstract: A storage cell employs two conventional N-channel MOS transistors and an inverted N-channel field-effect transistor along with an implanted polysilicon resistor and a resistor implanted under field oxide which functions as a junction field effect transistor. All of the transistors and a storage node as well as a voltage supply line are in one continuous moat region for a dense layout with a minimum of contacts. One MOS transistor is the access device connected between a bit line and the storage node with its gate connected to an address line. The other MOS transistor connects the storage node to the supply line and has its gate controlled by a second node which is connected to the supply line by a polycrystalline silicon strip which is the source-to-drain path of the inverted field-effect transistor; the gate of this device is a part of the moat which forms the storage node.

Abstract: A storage cell employs two conventional N-channel MOS transistors and an inverted N-channel field-effect transistor along with an implanted polysilicon resistor and a resistor implanted under field oxide which functions as a junction field effect transistor. All of the transistors and a storage node as well as a voltage supply line are in one continuous moat region for a dense layout with a minimum of contacts. One MOS transistor is the access device connected between a bit line and the storage node with its gate connected to an address line. The other MOS transistor connects the storage node to the supply line and has its gate controlled by a second node which is connected to the supply line by a polycrystalline silicon strip which is the source-to-drain path of the inverted field-effect transistor; the gate of this device is a part of the moat which forms the storage node.