Abstract: A first subset of components of a first set of pairs of complementary differential electrical signals representative of a numerical value expressed in a multi-bit thermometer code, is processed in accordance with a first set of Boolean functions to produce a first set of output electrical signal components , and a second subset of components of the first set of pairs of complementary differential electrical signals is processed in accordance with a second set of Boolean functions to produce a second set of output electrical signal components. The first and second subsets and the first and second sets of Boolean functions are such that the first and second sets of output electrical signal components when combined form a second set of pairs of complementary differential electrical signals representative of the same numerical value expressed in a second multi-bit code with fewer bits than the multi-bit thermometer code.

Abstract: A fully differential comparator includes a differential signal input, a differential reference input, and a differential signal output. Identical first and second gain stages are used in the differential comparator that each have a first single-ended input, a second single-ended input, and a differential output. The first single-ended inputs from the first and second gain stages form the differential signal input of the differential comparator. The second single-ended inputs from the first and second gain stages form the differential reference input of the differential comparator. The differential outputs of the first and second gain stages are cross-coupled to form the differential signal output of the differential comparator. The differential comparator can be used in conjunction with a conventional resistor string found in the front end of a flash ADC, but in a novel manner that prevents undesirable loading effects, as well as other problems associated with prior art single-ended comparators.

Abstract: An improvement is provided for current sources of the type having three transistors configured as follows: The bases of the first (Q1) and second (Q2) transistors are tied together. The collector of the first transistor (Q1) is coupled to a first voltage (V.sub.CC,V.sub.EE) via a first resistor (R1). The emitter of the first transistor (Q1) is coupled to a second voltage (V.sub.EE,V.sub.CC) via a second resistor (R2). The collector of the second transistor (Q2) produces the output current (I.sub.OUT). The emitter of the second transistor (Q2) is coupled to the second voltage (V.sub.EE,V.sub.CC) via a third resistor (R3). The base of the third transistor (Q3) is coupled, either directly or indirectly through a fourth transistor (Q4), to the collector of the first transistor (Q1). The collector of the third transistor (Q3) is connected to the first voltage (V.sub.CC,V.sub.EE) and the emitter of that transistor (Q3) is connected to the bases of the first (Q1) and second (Q2) transistors.