Abstract: An active matrix display device comprises an array of display elements (12), e.g. liquid crystal display elements, connected between sets of row and column address conductors (22,24). A display element electrode (20) is connected to an associated address conductor (22) of one set via two, parallel, switch means each of which comprises at least two, two-terminal, bi-directional, non-linear devices (30), for example, MIM type thin film diode devices, connected in series. A bidirectional, non-linear device (e.g. 30b) of each switch means (e.g. 30a, 30b) is shared by, and comprises a part of, a switch means (e.g. 30b, 30e) associated with a respective adjacent display element, there being in each switch means at least one non-linear device (e.g. 30a) between the shared device (30b) and the display element electrode (20).

Abstract: A matrix display device, suitable for displaying TV pictures, has a plurality of display elements (20) arranged in a matrix array and defined by electrodes (33 and 41) on opposing substrates with, for example, liquid crystal material (32) therebetween and with the display elements being individually controllable via switching elements (40) such as thin film transistors. Each display element is sub-divided into a plurality of sub-elements using a plurality of sub-electrodes (55) on one substrate which are each connected via a series capacitor (C.sub.X) to a switching element, the ratio of capacitances of the sub-elements to their respective series capacitors differing from one another. As applied voltage is increased, progressively more sub-elements are caused to change state providing in effect various grey scale levels. Display materials having comparatively sharp switching characteristics can be used.

Abstract: An active-matrix addressed LC display device includes a row and column array of display elements (12) each controlled by two transistors (TA, TB) selectively operable by switching signals applied to respective adjacent row conductors (R) to supply to the display elements data signals from column conductors (C). Each row conductor (R) is associated with two rowss of display elements (12) and each display element has a storage capacitor (SC). The storage capacitors of each row of display elements are provided by a respective supplementary conductor (RS) extending beneath, and insulated from, electrodes (14) of the display elements. A supplementary conductor is formed as an extension of a row conductor (R) associated with a preceding pair of adjacent rows of display elements. The supplementary conductors are interconnected to their row conductors at one end of the rows, and preferably, for redundancy purposes, also at the other end, by respective bridges (30, 31).

Abstract: A color display device has groups of liquid crystal display elements controlled by respective TFTs, the groups providing respective different color outputs, e.g. red, green and blue, and being either interspersed in a single panel with individual elements associated with color filter elements or in respective separate panels illuminated by differently colored light. The TFTs are of multilayer structure having semiconductor, gate insulator and gate layers. At least one layer thickness of the TFTs is different from group to group and is selected in accordance with the color light to which they are subjected so as to reduce absorption of that light, and consequently photo-induced currents in their semiconductor layers. Significantly reduced absorption is achievable by appropriate choice for example of semiconductor and insulator layer thicknesses based on optical interference considerations. The device can be used as a projection display device.

Abstract: A TFT is fabricated by providing on a substrate (10), and over a gate (12), a sequentially formed multi-layer structure consisting of a gate insulator layer (14), an intrinsic semiconductor, e.g. a-Si or polysilicon, layer (16) for the channel, a doped semiconductor, e.g. n type a-Si or polysilicon, layer (18) for source and drain contact regions and a passivating layer (20). The layer (18) extends completely over and covers the channel region of the layer (16). Thereafter, the portion (30) of layer (18) overlying the channel region is converted by a compensating doping implant to a highly resistive form separating the source and drain contact regions, and windows (22, 24) are defined in the passivating layer (20) into which source and drain contacts (26, 28) are deposited. In this way critical interfaces are protected from contamination. The TFT is suitable for use as a switching element in active matrix display devices, e.g. LC-TVs.

Abstract: In a multi-level circuit of the kind having two or more crossing conductive tracks (12, 14) on a substrate (16) separated at the region of the cross-over (21) by insulative material (20), for example for use in an active matrix display device requiring sets of mutually orthogonal conductors on a substrate for addressing switching elements (71) adjacent the cross-over regions connected to picture element electrodes (70) also carried on the substrate, at least one of the crossing tracks (12,14) is divided at the cross-over region into a plurality of mutually spaced conductive paths (24-26) connected electrically in parallel with one another.

Abstract: A method of manufacturing an active matrix addressed liquid crystal display device consisting of an array of individually controlled picture elements involves forming the electrodes after the address conductors by an autoregistration process using the address conductors to define edges of the electrodes. Opposite edges of the electrodes are thus aligned with repective facing edges of adjacent address conductors. The device's active area is thereby maximized and uncontrolled areas minimized.

Abstract: In a matrix display device, such as an LCD-TV, supply of data signals to each one of an array of display elements is controlled by respective switching devices circuits in response to applied switching signals. Each switching device circuit is fault-tolerant and has two branches each containing two series-connected transistors, e.g. TFTs, and connected in parallel between a data signal input and a display element electrode with the transistor gates being connected to a common switching signal input. For commonly-occuring transistor defects such a circuit can tolerate a defective transistor, thereby improving fabrication yields. Further transistor defects are accommodated for improved fault tolerance by provision of impedances (38) in the gate supply lines. The impedance may be resistors or active loads (41).

Abstract: The mask part 41 includes a substrate 1, a patterning means 40 and a photoemissive layer 6. The patterning means 40 includes a mask pattern 2, 3 of apertures 3 and masking areas 2 and a modifying layer 4. Ultraviolet radiation 56 is patterned by patterning means 40 before effecting electron emission 60 from the photoemissive layer 6. There is electron emission from over the apertures 3 and the masking areas 2 as the masking areas are partially transparent to incident ultraviolet radiation. The ultraviolet transmitted by the apertures and the masking areas is modified in intensity dependent on the thickness R of the modifying layer. The resuting electron emission 60 is in a patterned beam which forms a proximity effect corrected electron image of the mask pattern in the electron sensitive resist layer 63. The masking areas 2 of chromium and the modifying layer 4 of resist may be made by modifications of known methods of chromium deposition and resist exposure and development.

Abstract: A first masking layer on a semiconductor body is defined by exposing a layer of negative acting radiation sensitive resist to a radiation pattern through a mask. Doped regions are then formed at unmasked surface areas of the body. A layer of positive acting resist is provided on an insulating layer at the surface of the body, and a second masking layer is defined in this layer by exposure to the pattern radiation beam through the same mask. An insulating layer pattern which is accurately aligned above the doping region is then formed by etching the exposed parts of the layer. Alternatively, the same type of resist is used at both exposure stages. By adjusting the resist processing, the second masking layer is made larger than the first masking layer. In this case, the second masking layer is used to define an oxygen mask before oxidizing the exposed surface of the body to form an accurately aligned oxide layer pattern.

Abstract: A method of manufacturing an insulated gate field effect transistor includes the provision of a first masking layer on a semiconductor body followed by the introduction of a dopant characteristic of the conductivity type of the semiconductor body into unmasked areas to form a channel stopper. The unmasked areas are then oxidized to form an inset oxide layer. Subsequently, the masking layer is removed to expose a window in the oxide layer, and then a second masking layer is provided on the oxide layer. The second masking layer includes a second window extending into the first window so that the sides of the second window are situated within the first window. The sides of the second window determine the width of the channel region in a subsequent implantation of ions characteristic of the conductivity type of the channel region. Consequently, the channel region is spaced apart from the channel stoppers, and a very narrow channel region, for example 2 micrometers, is provided.

Abstract: A method of manufacturing a semiconductor device is set forth in which a masking layer is formed on part of the surface of a deposited layer of a relatively high resistivity polycrystalline semiconductor material being present on an insulating layer provided at a surface of a semiconductor body or portion thereof. A relatively low resistivity conductive region having a substantially uniform narrow line width is defined in the polycrystalline layer by effecting a diffusion process to laterally diffuse a doping element into a portion of the polycrystalline layer underlying an edge portion of the masking layer without diffusing the doping element through the insulating layer into the semiconductor body or portion thereof.

Abstract: A method of manufacturing a semiconductor device in which a masking layer is formed on part of the surface of a deposited layer of relatively high resistivity polycrystalline semiconductor material present on an insulating layer provided at a surface of a semiconductor body or body part and a relatively low resistivity conductive region having a substantially uniform narrow line width is defined in the polycrystalline layer by effecting a diffusion process to laterally diffuse a doping element into a portion of the polycrystalline layer underlying an edge portion of the masking layer without diffusing the doping element through the insulating layer into the semiconductor body or body part.

Abstract: A method of manufacturing an electronic device, comprising a plurality of closely spaced conductive layers on a substrate, said method comprising the steps of depositing said substrate a layer of polycrystalline semiconductor material, providing at least one aperture defined in and extending through said polycrystalline layer, effecting a material treatment via an exposed edge of said polycrystalline layer in said aperture in the presence of a masking layer on said polycrystalline layer, said treatment being effected to convert a narrow strip portion of the polycrystalline layer of substantially uniform width and underlying the masking layer adjacent the aperture into material insoluble in an etchant specific for the untreated part of said polycrystalline layer, removing said masking layer and selectively removing, with the use of said etchant, the untreated polycrystalline semiconductor material to leave a narrow strip of material present on and raised above the substrate, and effecting a deposition of condu