Abstract: Radiation detectors are mounted in an optic focal plane of an infrared radiation sensor system. The radiation detectors produce output signals indicating detected radiation. The output signals are sampled by a sample-and-hold circuit and passed to a 1-bit comparator. The comparator produces a 1-bit signal at a high voltage level for samples of the output signal that are greater than a reference voltage and at a low voltage level for samples of the output signal that are less than the reference voltage. In this manner, the comparator reduces the effects of any gamma spikes on the measurement of intensity of radiation. The 1-bit signal is less susceptible to effects of interference than analog signals in conventional systems and the 1-bit comparator produces this 1-bit signal without consuming a great deal of electrical power. A multiplexor carries such 1-bit signals from the focal plane to a processor over less wires than in conventional systems.

Abstract: A processor for an FM/CW sensor divides the sweep periods of the sensor into a number of subsweep intervals, measures the received power within a multiplicity of frequency windows during each of the subsweep intervals, and then performs a spectrum analysis of the power measurements in each frequency window to characterize the reflectors in the corresponding range bins of the FM/CW sensor footprint.

Abstract: A scanning sensor system for simultaneously correcting time varying view angle errors and suppressing sensor noise. The system comprises a scanning sensor producing a sensor output signal corresponding to an actual view angle which differs from a desired view angle by a jitter angle error. The jitter angle error is detected by a detector and a corresponding jitter error signal is generated. Data samples of the sensor output signal are sequentially stored in a data memory. The system also comprises a coefficient memory for storing a plurality of sets of weighting coefficients, each weighting coefficient set being defined by a noise suppression filter impulse response. One of the plurality of weighting coefficient sets is selected in accordance with the jitter error signal following which each one of the sequentially stored data samples is multiplied by a respective weighting coefficient from the selected set of weighting coefficients.

Abstract: A scanning sensor system scans a detector array across a field of view, the array comprising a plurality of infrared detector elements which are positioned in the array with spaces interspersed therebetween. The system scans separate detector elements across separate portions of the field of view at a slow scan rate and then rapidly steps to scan a different portion of the field of view, thereby permitting a high frame rate despite a low target sensing scan rate to lower the required total sample rate, reduce processing circuit complexity, and reduce the number of required interconnections between the focal plane array and on-gimbal processing circuitry.

Abstract: A radar signal processor and methods of operating same for determining the differential sideband power of reflected energy received in a frequency window by a radar receiver, which processor contains a generator of orthogonal signals, a mixer for multiplying these orthogonal signals times quadrature signals, an integrating circuit for integrating the mixer outputs over a predetermined time interval, a multiplier for multiplying the integrals from the integrating circuit together, and a circuit to average the products from the multiplier over time.

Abstract: A scanning infrared sensor scans an array of detector elements across a field of view and samples the detector elements at a predetermined rate. The detector elements are sampled with a common sample frequency and with predetermined time phase values, are processed through delay elements such that the delayed detector output signal values are out of time phase, and are supplied to a multiplexer. The multiplexer produces a series of discrete signals at equal time intervals having an effective sample rate which is a multiple of the individual detector element sample rate, thereby reducing the complexity of processing circuitry, the number of interconnections required between the focal plane array and on-gimbal circuitry, and the size and weight of delay elements.

Abstract: The radar signal processor multiplies in real time samples from a radar system and coefficients representing desired frequency windows to be examined and integrates those products over a time period related to the particular frequency window in order to determine the amount of energy in the different frequency windows of the different range bins of the radar system.

Abstract: An FM/CW radar linearization network provides target identification data discriminating a target from background reflections and/or false targets by compensating for random variations in the linearity of the frequency sweep of the radar transmitter in the processing of the radar receiver signal, the latter being characteristic of the range and physical size of the target. Linearization is achieved by sampling the transmitter signal, generating an error signal proportional to and indicative of any deviations in the frequency sweep of the transmitter from that for linear operation, and applying that error signal to correct the target data signal, thereby frequency normalizing the same for processing and utilization.

Abstract: Signals in the form of pulses generated by a plurality of signal sources are received at two spaced receivers, and following initial filtering (if any), are stored, in chronological order of receipt, in memories associated with each receiver. Each pulse so stored has associated therewith time data which is the time of its arrival at the receiver. The difference between the time data of the first pulse stored in the first memory and the time data of each, or selected ones, of the pulses in turn in the second memory is determined, and then compared with a preselected range of time data. A preselected numerical quantity is then added to a specific address location in an accumulator whenever the time difference satisfies the preselected range. Each satisfactory time difference has a unique address location in the accumulator. The above steps are then repeated for each singal in the first memory.