Abstract: A method of reducing read errors in a non-volatile memory device that result from bit-line or word-line disturb conditions generated by erase operations includes selecting a subset of a memory array for refresh after each erase operation. A pointer to the refresh target section is updated as part of the method to direct the refresh operation to the appropriate subset of the memory array. Refresh may be performed subsequent to an erase operation or concurrently therewith. By distributing the time consumed by refresh operations over many erase operations so the relative refresh time for any one erase becomes small.

Abstract: A method of reducing read errors in a non-volatile memory device that result from bit-line or word-line disturb conditions generated by erase operations includes selecting a subset of a memory array for refresh after each erase operation. A pointer to the refresh target section is updated as part of the method to direct the refresh operation to the appropriate subset of the memory array. Refresh may be performed subsequent to an erase operation or concurrently therewith. By distributing the time consumed by refresh operations over many erase operations so the relative refresh time for any one erase becomes small.

Abstract: A method and system are disclosed for verifying memory cell erasure, which may be employed in association with a dual bit memory cell architecture. The method includes selectively verifying proper erasure of one of a first bit of the cell and a second bit of the cell, determining that the dual bit memory cell is properly erased if the first and second bits of the cell are properly erased, and selectively erasing at least one of the first and second bits of the cell if one of the first and second bits is not properly erased. The method may also comprise selectively re-verifying proper erasure of one of the first and second bits after selectively erasing at least one of the first and second bits.