Patents by Inventor Keith J. Hansen
Keith J. Hansen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6228186Abstract: Improved targets for use in DC_magnetron sputtering of aluminum or like metals are disclosed for forming metallization films having low defect densities. Methods for manufacturing and using such targets are also disclosed. Conductivity anomalies such as those composed of metal oxide inclusions can induce arcing between the target surface and the plasma. The arcing can lead to production of excessive deposition material in the form of splats or blobs. Reducing the content of conductivity anomalies and strengthening the to-be-deposited material is seen to reduce production of such splats or blobs. Other splat limiting steps include smooth finishing of the target surface and low-stress ramp up of the plasma.Type: GrantFiled: October 14, 1999Date of Patent: May 8, 2001Assignee: Applied Materials, Inc.Inventors: Vikram Pavate, Keith J. Hansen, Glen Mori, Murali Narasimhan, Seshadri Ramaswami, Jaim Nulman
-
Patent number: 6171455Abstract: Improved targets for use in DC_magnetron sputtering of aluminum or like metals are disclosed for forming metallization films having low defect densities. Methods for manufacturing and using such targets are also disclosed. Conductivity anomalies such as those composed of metal oxide inclusions can induce arcing between the target surface and the plasma. The arcing can lead to production of excessive deposition material in the form of splats or blobs. Reducing the content of conductivity anomalies and strengthening the to-be-deposited material is seen to reduce production of such splats or blobs. Other splat limiting steps include smooth finishing of the target surface and low-stress ramp up of the plasma.Type: GrantFiled: October 14, 1999Date of Patent: January 9, 2001Assignee: Applied Materials Inc.Inventors: Vikram Pavate, Keith J. Hansen, Glen Mori, Murali Narasimhan, Seshadri Ramaswami, Jaim Nulman
-
Patent number: 6126791Abstract: Improved targets for use in DC.sub.-- magnetron sputtering of aluminum or like metals are disclosed for forming metallization films having low defect densities. Methods for manufacturing and using such targets are also disclosed. Conductivity anomalies such as those composed of metal oxide inclusions can induce arcing between the target surface and the plasma. The arcing can lead to production of excessive deposition material in the form of splats or blobs. Reducing the content of conductivity anomalies and strengthening the to-be-deposited material is seen to reduce production of such splats or blobs. Other splat limiting steps include smooth finishing of the target surface and low-stress ramp up of the plasma.Type: GrantFiled: October 14, 1999Date of Patent: October 3, 2000Assignee: Applied Materials, Inc.Inventors: Vikram Pavate, Keith J. Hansen, Glen Mori, Murali Narasimhan, Seshadri Ramaswami, Jaim Nulman
-
Patent number: 6113699Abstract: In one embodiment, a method of forming a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree. C.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas.Type: GrantFiled: November 26, 1997Date of Patent: September 5, 2000Assignee: LSI Logic CorporationInventor: Keith J. Hansen
-
Patent number: 6001227Abstract: Improved targets for use in DC.sub.-- magnetron sputtering of aluminum or like metals are disclosed for forming metallization films having low defect densities. Methods for manufacturing and using such targets are also disclosed. Conductivity anomalies such as those composed of metal oxide inclusions can induce arcing between the target surface and the plasma. The arcing can lead to production of excessive deposition material in the form of splats or blobs. Reducing the content of conductivity anomalies and strengthening the to-be-deposited material is seen to reduce production of such splats or blobs. Other splat limiting steps include smooth finishing of the target surface and low-stress ramp up of the plasma.Type: GrantFiled: November 26, 1997Date of Patent: December 14, 1999Assignee: Applied Materials, Inc.Inventors: Vikram Pavate, Keith J. Hansen, Glen Mori, Murali Narasimhan, Seshadri Ramaswami, Jaim Nulman
-
Patent number: 5914001Abstract: In one embodiment, a method of forming a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree. C.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas.Type: GrantFiled: November 26, 1997Date of Patent: June 22, 1999Assignee: LSI Logic CorporationInventor: Keith J. Hansen
-
Patent number: 5853804Abstract: In one embodiment, a method of forming a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas.Type: GrantFiled: May 6, 1997Date of Patent: December 29, 1998Assignee: LSI Logic CorporationInventor: Keith J. Hansen
-
Patent number: 5681613Abstract: A method for filtering process gases prior to said process gases being allowed to enter a CVD chamber is provided in order to ensure high purity of the process gases. In one embodiment, the process gases are filtered with a first filter located in a first section of a gas line being isolated by valves at both ends of the gas line section. Further filtering by a second filter occurs in a downstream gas line section.Type: GrantFiled: February 17, 1995Date of Patent: October 28, 1997Assignee: LSI Logic CorporationInventor: Keith J. Hansen
-
Patent number: 5391394Abstract: In one embodiment, a method of forming a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree. C.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas.Type: GrantFiled: July 29, 1991Date of Patent: February 21, 1995Assignee: LSI Logic CorporationInventor: Keith J. Hansen
-
Patent number: 5211796Abstract: Walls of a CVD chamber are automatically controlled to be heated to above 65.degree. C. during etching of the chamber walls with NF.sub.3. Any condensation of reaction products on the chamber walls is avoided, since, at the relatively high chamber wall temperature, these reaction products are volatile and are purged away with the NF.sub.3. The apparatus is programmed to automatically carry out this heating and gas injecting process.Type: GrantFiled: December 12, 1991Date of Patent: May 18, 1993Assignee: LST Logic CorporationInventor: Keith J. Hansen
-
Patent number: 5203956Abstract: During the cleaning of CVD chamber walls with an etch gas of NF.sub.3, the reaction chamber walls are heated to above 65.degree. C. while maintaining a relatively low chamber pressure during etching of the chamber with NF.sub.3. Any reaction of the NF.sub.3 with the quartz (SiO.sub.2) walls of the chamber, and with any reaction by-products remaining in the chamber, will not condense on the walls of the chamber, since, at this relatively high temperature, these reaction products will be volatile and will be purged away with the NF.sub.3.Type: GrantFiled: November 18, 1991Date of Patent: April 20, 1993Assignee: LSI Logic CorporationInventor: Keith J. Hansen
-
Patent number: 5180432Abstract: In one embodiment, an apparatus programmed to automatically form a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree. C.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas.Type: GrantFiled: October 2, 1990Date of Patent: January 19, 1993Assignee: LSI Logic CorporationInventor: Keith J. Hansen
-
Patent number: 5123375Abstract: A structure for filtering process gases prior to said process gases being allowed to enter a CVD chamber includes improved filter and control means to ensure high purity of the process gases. In one embodiment, a first filter means is located in a first section of a gas line being isolated by valves at both ends of the gas line section. A second filter means is located in a downstream gas line section for further filtering.Type: GrantFiled: October 2, 1990Date of Patent: June 23, 1992Assignee: LSI Logic CorporationInventor: Keith J. Hansen