Patents by Inventor Keith Jarreau
Keith Jarreau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9466572Abstract: An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.Type: GrantFiled: October 16, 2012Date of Patent: October 11, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Allan T. Mitchell, Keith Jarreau
-
Patent number: 9406621Abstract: An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.Type: GrantFiled: June 10, 2010Date of Patent: August 2, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Allan T. Mitchell, Keith Jarreau
-
Patent number: 9257440Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.Type: GrantFiled: May 2, 2014Date of Patent: February 9, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
-
Patent number: 8946805Abstract: A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.Type: GrantFiled: August 6, 2009Date of Patent: February 3, 2015Assignee: Texas Instruments IncorporatedInventors: Jozef C. Mitros, Keith Jarreau, Pinghai Hao
-
Publication number: 20140239409Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.Type: ApplicationFiled: May 2, 2014Publication date: August 28, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
-
Patent number: 8748235Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.Type: GrantFiled: August 8, 2012Date of Patent: June 10, 2014Assignee: Texas Instruments IncorporatedInventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
-
Publication number: 20120313180Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.Type: ApplicationFiled: August 8, 2012Publication date: December 13, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
-
Publication number: 20120228724Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.Type: ApplicationFiled: March 11, 2011Publication date: September 13, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
-
Patent number: 8258586Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.Type: GrantFiled: March 11, 2011Date of Patent: September 4, 2012Assignee: Texas Instruments IncorporatedInventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
-
Publication number: 20110303959Abstract: An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.Type: ApplicationFiled: June 10, 2010Publication date: December 15, 2011Applicant: Texas Instruments IncorporatedInventors: Allan T. Mitchell, Keith Jarreau
-
Publication number: 20100032744Abstract: A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.Type: ApplicationFiled: August 6, 2009Publication date: February 11, 2010Applicant: Texas Instruments IncorporatedInventors: Jozef C. Mitros, Keith Jarreau, Pinghai Hao