Patents by Inventor Keith Joyner

Keith Joyner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050029560
    Abstract: Methods and apparatus are disclosed for selectively inducing stress in a semiconductor device, wherein a first region of a substrate is implanted so as to induce stress in a second region. An electrical device is formed at least partially in the second region, wherein the induced stress therein may improve one or more operational characteristics of the device, such as channel region carrier mobility.
    Type: Application
    Filed: September 7, 2004
    Publication date: February 10, 2005
    Inventors: Christoph Wasshuber, Keith Joyner
  • Patent number: 5863827
    Abstract: A shallow trench isolation (STJ) (10) is used to isolate two active regions (12) from each other. The advantage of STI (10) is that the upper corners (14) are rounded. Rounding of the upper corners (14) is accomplished using an oxide deglaze prior to sidewall oxidation of the trench which undercuts the pad oxide (20) from the pad nitride (22). The allows the sidewall oxidation process to form a thicker oxide at upper corners (14) which in turn, rounds the corners. Rounded corners (14) minimum the electric field strength induced by the geometry. As a result, the Vt lowering that occurs in prior art STI structures is minimized and off-state leakage due to the inherent parasitic transistor at the upper corner is reduced.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: January 26, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Keith Joyner