Patents by Inventor Keith Klayman

Keith Klayman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220350500
    Abstract: An apparatus is described. The apparatus includes a processor. The processor includes a memory controller to read and write from a memory. The memory controller includes error correction coding (ECC) circuitry to correct errors in data read from the memory. The processor includes register space to track read data error information. The processor includes an embedded controller. The processor includes local memory coupled to the embedded controller. The embedded controller is to read the read data error information and store the read data error information in the local memory.
    Type: Application
    Filed: June 30, 2022
    Publication date: November 3, 2022
    Inventors: Wei P. CHEN, Theodros YIGZAW, Sarathy JAYAKUMAR, Anthony LUCK, Deep K. BUCH, Rajat AGARWAL, Kuljit S. BAINS, John G. HOLM, Brent CHARTRAND, Keith KLAYMAN
  • Patent number: 9690366
    Abstract: A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: June 27, 2017
    Assignee: Intellectual Ventures Holding 81 LLC
    Inventors: Andrew Read, Sameer Halepete, Keith Klayman
  • Publication number: 20160357247
    Abstract: A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.
    Type: Application
    Filed: August 19, 2016
    Publication date: December 8, 2016
    Inventors: Andrew Read, Sameer Halepete, Keith Klayman
  • Patent number: 9436264
    Abstract: A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: September 6, 2016
    Assignee: Intellectual Ventures Holding 81 LLC
    Inventors: Andrew Read, Sameer Halepete, Keith Klayman
  • Publication number: 20150145580
    Abstract: Apparatus including functional components of circuitry defined on a semiconductor chip, the functional components including a component having modifiable operating characteristics, a performance measuring circuit providing an output indicative of operating characteristics of the circuitry defined on the semiconductor chip during operation of the circuitry, and computer implemented software means for controlling a value for an operating characteristic of the component having modifiable operating characteristics in response to the output provided by the performance measuring circuit.
    Type: Application
    Filed: December 30, 2008
    Publication date: May 28, 2015
    Applicant: TRANSMETA CORPORATION
    Inventors: Godfrey P. D'Souza, Keith Klayman
  • Patent number: 8806247
    Abstract: A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 12, 2014
    Inventors: Sameer Halepete, H. Peter Anvin, Zongjian Chen, Godfrey P. D'Souza, Marc Fleischmann, Keith Klayman, Thomas Lawrence, Andrew Read
  • Patent number: 8566627
    Abstract: A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: October 22, 2013
    Inventors: Sameer Halepete, H. Peter Anvin, Zongjian Chen, Godfrey P. D'Souza, Marc Fleischmann, Keith Klayman, Thomas Lawrence, Andrew Read
  • Publication number: 20130132749
    Abstract: A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.
    Type: Application
    Filed: December 21, 2012
    Publication date: May 23, 2013
    Inventors: Sameer Halepete, H. Peter Anvin, Zongjian Chen, Godfrey P. D'Souza, Marc Fleischmann, Keith Klayman, Thomas Lawrence, Andrew Read
  • Publication number: 20110107131
    Abstract: A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.
    Type: Application
    Filed: January 10, 2011
    Publication date: May 5, 2011
    Inventors: Andrew Read, Sameer Halepete, Keith Klayman
  • Patent number: 7870404
    Abstract: A method for reducing power utilized by a processor including determining that a processor is transitioning from a computer mode to a mode in which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: January 11, 2011
    Inventors: Andrew Read, Sameer Halepete, Keith Klayman
  • Patent number: 7810002
    Abstract: A method for securing a scan chain architecture by performing an authentication operation through a trusted software layer to authorize use of a protected scan chain.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: October 5, 2010
    Inventors: David Dunn, Keith Klayman
  • Publication number: 20100011233
    Abstract: A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 14, 2010
    Inventors: Sameer Halepete, H. Peter Anvin, Zongjian Chen, Godfrey P. D'Souza, Marc Fleischmann, Keith Klayman, Thomas Lawrence, Andrew Read
  • Publication number: 20090307546
    Abstract: A method for securing a scan chain architecture by performing an authentication operation through a trusted software layer to authorize use of a protected scan chain.
    Type: Application
    Filed: August 19, 2009
    Publication date: December 10, 2009
    Inventors: David Dunn, Keith Klayman
  • Patent number: 7600166
    Abstract: A method for securing a scan chain architecture by performing an authentication operation through a trusted software layer to authorize use of a protected scan chain.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: October 6, 2009
    Inventors: David Dunn, Keith Klayman
  • Patent number: 7596708
    Abstract: A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: September 29, 2009
    Inventors: Sameer Halepete, H. Peter Anvin, Zongjian Chen, Godfrey P. D'Souza, Marc Fleischmann, Keith Klayman, Thomas Lawrence, Andrew Read
  • Patent number: 7472033
    Abstract: Apparatus including functional components of circuitry defined on a semiconductor chip, the functional components including a component having modifiable operating characteristics, a performance measuring circuit providing an output indicative of operating characteristics of the circuitry defined on the semiconductor chip during operation of the circuitry, and computer implemented software means for controlling a value for an operating characteristic of the component having modifiable operating characteristics in response to the output provided by the performance measuring circuit.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: December 30, 2008
    Assignee: Transmeta Corporation
    Inventors: Godfrey P. D'Souza, Keith Klayman
  • Publication number: 20070294555
    Abstract: A method for reducing power utilized by a processor including determining that a processor is transitioning from a computer mode to a mode in which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.
    Type: Application
    Filed: August 21, 2007
    Publication date: December 20, 2007
    Inventors: Andrew Read, Sameer Halepete, Keith Klayman
  • Patent number: 7260731
    Abstract: A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: August 21, 2007
    Assignee: Transmeta Corporation
    Inventors: Andrew Read, Sameer Halepete, Keith Klayman
  • Patent number: 7100061
    Abstract: A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: August 29, 2006
    Assignee: Transmeta Corporation
    Inventors: Sameer Halepete, H. Peter Anvin, Zongjian Chen, Godfrey P. D'Souza, Marc Fleischmann, Keith Klayman, Thomas Lawrence, Andrew Read
  • Publication number: 20020116650
    Abstract: A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.
    Type: Application
    Filed: January 18, 2000
    Publication date: August 22, 2002
    Inventors: Sameer Halepete, H. Peter Anvin, Zongjian Chen, Godfrey P. D'Souza, Marc Fleischman, Keith Klayman, Thomas Lawrence, Andrew Read