Patents by Inventor Keith Kwong Hon Wong

Keith Kwong Hon Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11152300
    Abstract: An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Yan Zun Li, Keith Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 10699949
    Abstract: A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Keith Kwong Hon Wong, Wonwoo Kim, Praneet Adusumilli
  • Patent number: 10490501
    Abstract: Aspects of the present disclosure include a method for forming a contact on a semiconductor device, the semiconductor device including a conductive region disposed over a substrate, the method comprising: depositing a dielectric material on the substrate; forming an opening in the dielectric material to expose the conductive region; forming a barrier layer on a lower surface and sidewalls of the opening in the dielectric material, the barrier layer terminating below an upper surface of the dielectric material and surrounding a lower portion of the opening; depositing cobalt in the lower portion of the opening, the cobalt terminating at an upper surface of the barrier layer; depositing tungsten to fill the opening to at least the upper surface of the dielectric material; and planarizing the upper surface of the dielectric material with the tungsten in the opening.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: November 26, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jim Shih-Chun Liang, Keith Kwong Hon Wong
  • Publication number: 20190237365
    Abstract: A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal.
    Type: Application
    Filed: April 9, 2019
    Publication date: August 1, 2019
    Inventors: Keith Kwong Hon Wong, Wonwoo Kim, Praneet Adusumilli
  • Patent number: 10347529
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to interconnect structures and methods of manufacture. The structure includes a metallization feature comprising a fill material and formed within a dielectric layer; at least one cap covering the fill material of the metallization feature, the at least one cap is comprised of a material different than the fill material of the metallization feature; and an interconnect structure in electrical contact with the metallization feature.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jim Shih-Chun Liang, Keith Kwong Hon Wong
  • Patent number: 10319633
    Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brett H. Engel, Domingo A. Ferrer, Arun Vijayakumar, Keith Kwong Hon Wong
  • Patent number: 10304735
    Abstract: A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 28, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Keith Kwong Hon Wong, Wonwoo Kim, Praneet Adusumilli
  • Publication number: 20190103310
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to interconnect structures and methods of manufacture. The structure includes a metallization feature comprising a fill material and formed within a dielectric layer; at least one cap covering the fill material of the metallization feature, the at least one cap is comprised of a material different than the fill material of the metallization feature; and an interconnect structure in electrical contact with the metallization feature.
    Type: Application
    Filed: October 4, 2017
    Publication date: April 4, 2019
    Inventors: Jim Shih-Chun LIANG, Keith Kwong Hon Wong
  • Publication number: 20190096679
    Abstract: Structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. A gate cavity is formed in a dielectric layer that includes a bottom surface and a plurality sidewalls that extend to the bottom surface. A gate dielectric layer is formed at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A fill metal layer is deposited inside the gate cavity after the work function metal layer is deposited. The fill metal layer is formed in direct contact with the work function metal layer.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 28, 2019
    Inventors: Balaji Kannan, Bala Haran, Vimal K. Kamineni, Sungkee Han, Neal Makela, Suraj K. Patil, Pei Liu, Chih-Chiang Chang, Katsunori Onishi, Keith Kwong Hon Wong, Ruilong Xie, Chanro Park, Min Gyu Sung
  • Patent number: 10192822
    Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen into the structure.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Domingo A. Ferrer, Kriteshwar K. Kohli, Siddarth A. Krishnan, Joseph F. Shepard, Jr., Keith Kwong Hon Wong
  • Patent number: 10170359
    Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brett H. Engel, Domingo A. Ferrer, Arun Vijayakumar, Keith Kwong Hon Wong
  • Publication number: 20180374746
    Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.
    Type: Application
    Filed: August 31, 2018
    Publication date: December 27, 2018
    Inventors: Brett H. Engel, Domingo A. Ferrer, Arun Vijayakumar, Keith Kwong Hon Wong
  • Publication number: 20180374749
    Abstract: A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal.
    Type: Application
    Filed: June 22, 2017
    Publication date: December 27, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Keith Kwong Hon WONG, Wonwoo KIM, Praneet ADUSUMILLI
  • Patent number: 10096609
    Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by changing the crystalline structure to a tetragonal tungsten silicon layer.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: October 9, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicolas L. Breil, Domingo A. Ferrer, Keith Kwong Hon Wong
  • Patent number: 10090240
    Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming an opening in a low-k dielectric layer; filling the opening with a high-k dielectric material; patterning the low-k dielectric layer outside of the opening and the high-k dielectric layer to form an interconnect opening within the low-k dielectric layer and a capacitor opening within the high-k dielectric layer; and filling the interconnect opening and the capacitor opening with a metal to form an interconnect in the low-k dielectric layer and a capacitor in the high-k dielectric layer.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: October 2, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Baozhen Li, Chih-Chao Yang, Keith Kwong Hon Wong
  • Patent number: 10020256
    Abstract: A structure including a dual damascene feature in a dielectric layer, the dual damascene feature including a first via, a second via, and a trench, the first via, the second via being filled with a conductive material, a fuse line at the bottom of the trench on top of the first via and the second via, the fuse line including the conductive material; an insulating layer on top of the fuse line and along a sidewall of the trench, and a fill material on top of the insulating layer and substantially filling the trench.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chad M. Burke, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
  • Publication number: 20180166385
    Abstract: Aspects of the present disclosure include a method for forming a contact on a semiconductor device, the semiconductor device including a conductive region disposed over a substrate, the method comprising: depositing a dielectric material on the substrate; forming an opening in the dielectric material to expose the conductive region; forming a barrier layer on a lower surface and sidewalls of the opening in the dielectric material, the barrier layer terminating below an upper surface of the dielectric material and surrounding a lower portion of the opening; depositing cobalt in the lower portion of the opening, the cobalt terminating at an upper surface of the barrier layer; depositing tungsten to fill the opening to at least the upper surface of the dielectric material; and planarizing the upper surface of the dielectric material with the tungsten in the opening.
    Type: Application
    Filed: February 9, 2018
    Publication date: June 14, 2018
    Inventors: Jim Shih-Chun Liang, Keith Kwong Hon Wong
  • Patent number: 9997518
    Abstract: In one embodiment, a method of making a semiconductor device includes: forming a substrate; forming an nFET transistor and a pFET transistor on the substrate; wherein forming the nFET transistor comprises first depositing several first layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several first layers; wherein forming the pFET transistor comprises first depositing several second layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several second layers.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Keith Kwong Hon Wong
  • Publication number: 20180138123
    Abstract: Aspects of the present disclosure include a semiconductor device which includes a dielectric layer deposited over a conductive region and an interconnect electrically connecting the conductive region with a top surface of the dielectric layer. The interconnect includes a barrier layer extending from an interior of the dielectric layer to the conductive region and covering the conductive region. The barrier layer encases a cobalt plug. The interconnect includes a tungsten cap on an upper surface of the cobalt plug. The tungsten cap is coplanar with an upper surface of the dielectric layer. A method of manufacturing the semiconductor device is also provided.
    Type: Application
    Filed: November 15, 2016
    Publication date: May 17, 2018
    Inventors: Jim Shih-Chun Liang, Keith Kwong Hon Wong
  • Patent number: 9960161
    Abstract: In one embodiment, a method of making a semiconductor device includes: forming a substrate; forming an nFET transistor and a pFET transistor on the substrate; wherein forming the nFET transistor comprises first depositing several first layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several first layers; wherein forming the pFET transistor comprises first depositing several second layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several second layers.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: May 1, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Keith Kwong Hon Wong