Abstract: Certain aspects of a multi-channel signal synchronizer may comprise receiving a plurality of clock signals from a plurality of clock signal sources, wherein a portion of the received plurality of clock signals may be out of synchronization with a remaining portion of the received plurality of clock signals. A plurality of data signals may be received from a plurality of data signal sources, wherein a portion of the received plurality of data signals may be out of synchronization with a remaining portion of the received plurality of data signals. The received portion of plurality of clock signals and data signals may be synchronized to the received remaining portion of plurality of clock signals and data signals utilizing bit alignment and sample alignment. A plurality of synchronized output signals may be generated based on the synchronized received plurality of clock signals and synchronized received plurality of data signals.

Abstract: A system and method of verifying the format of a simulated signal produced during the simulation of an electronic circuit is disclosed. One aspect of the present invention includes a method of extracting timing information from a single simulated serial digital audio signal that comprises both data and clock. An embodiment of the present invention may verify operation of the simulated electronic circuit by setting the value of a first simulated signal according to predetermined events that occur in a second simulated signal. The second simulated signal may be parsed using timing information extracted from the second simulated signal, and the format of the second simulated signal may be matched against a predetermined format based upon the results of the parsing.

Abstract: Provided is a system and method for muting zero level pulse code modulated (PCM) samples. PCM samples are received as inputs to a digital to analog converter (DAC) including a PCM input module and a mapping module. The method includes monitoring a level of the PCM samples received as inputs to the PCM input module and sensing consecutive zero level PCM samples from among the monitored input PCM samples. The method also includes muting a PCM input to the mapper when a predetermined number of zero level PCM samples have been sensed.

Abstract: Provided is a system and method for converting digital data audio data audio data that has a predetermined input sample rate, into an analog data signal. A system includes a digital to analog converter (DAC) including a digital processing portion configured to receive as an input the digital audio data and timing information, the timing information being representative of a time base of the input sample rate. The digital processing portion is similarly configured to digitally process the digital audio data and the timing information to produce serialized output data. The DAC also includes an analog processing portion configured to convert serialized data to an analog format. The digital processing portion operates in accordance with at least one clock having a corresponding clock rate wherein the corresponding clock rate is unrelated to the input sample rate.

Abstract: An audio receiver FIFO memory buffer in the serial digital video interface allows improved timing synchronization between video and audio information. Furthermore, it eliminates unpleasant sound effects when multiple data samples are skipped or repeated in series. This FIFO receiver buffer receives data at an input write-data rate filling up the memory storage cells therein. An output read-data signal clocks the data out of the memory storage cells. The FIFO's fullness is monitored and maintained, in response to an external signal, to within a specified range delimited by an upper and a lower threshold. If the FIFO buffer fullness is below the range's lower threshold, then the FIFO's read address pointer is held so that the immediately preceding read out data element is read out again, but only once. On the other hand, the FIFO buffer fullness is over the range's upper limit, then the FIFO's write address pointer is held so that the immediately preceding written in data element is written over, but only once.