Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.

Abstract: In some embodiments, an apparatus includes processing circuitry that includes a plurality of different components configured to perform operations to generate execution results for instructions executed by the apparatus. In some embodiments the apparatus includes front-end circuitry configured to retrieve a plurality of instructions for execution and, based on identification of one or more instruction characteristics of the plurality of instructions, selectively disable one or more portions of the processing circuitry for one or more cycles during execution of the plurality of instructions. In some embodiments, this may reduce power consumption by the apparatus.

Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.

Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.

Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.

Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.

Abstract: The present invention minimizes power consumption and processing time in a very long instruction word digital signal processor by identifying certain blocks of instructions and placing them in a small, fast buffer for subsequent retrieval and execution. A decoder unit decodes a prefetch instruction flag bit that indicates when instructions are to be prefetched and placed into the buffer. The decoder unit signals a control unit, which sends the instruction code from a memory unit to the buffer and maintains an address mapping table and a program counter. The control unit also sets a select input on a multiplexer to indicate that the multiplexer is to output the prefetch instructions it receives from the buffer. The multiplexer outputs the prefetch instructions to an instruction register that sends the prefetch instructions to appropriate functional units for execution.

Abstract: A space vector data path for integrating SIMD scheme into a general-purpose programmable processor. The programmable processor uses a mode field in each instruction to specify, for each instruction, whether an operand is processed in either one of vector or scalar modes. The programmable processor also has a plurality of sub-processing units for receiving the operand and, responsive to an instruction as specified by the mode field in each instruction, for processing the operand in either one of the vector or scalar modes, wherein the vector mode indicates to the plurality of sub-processing units that there are a plurality of elements within the operand and the scalar mode indicates to the plurality of sub-processing units that there is but one element within the operand. For the vector mode, each element is processed by one of the sub-processing units concurrently to generate a vector result.

Abstract: The STREAMER FOR RISC DIGITAL SIGNAL PROCESSOR shown herein allows a CPU 46 to interface with a memory 60 via data registers 50. Pre-fetch and post-store of the correct address is determined by an address generator 58 according to a rule determined by a context register 52. An index indicative of this address is stored in an index register 54. The data, context, and index registers together form a streamer 56, streaming data between the CPU 46 and data memory 60. The rule of the context register 52 also drives a converter 62 for converting data between memory format and register format. The speed and flexibility of a RISC device is combined with the intensive memory access of a digital signal processor.

Abstract: A debug port in accordance with the invention provides circuitry for enabling system (hardware and software) development within an inaccessible computer processor. In one embodiment, a debug port is incorporated within the internal logic of a single-chip, reduced instruction set signal processor referred to as the signal processor. A fully implemented debug port is comprised of five interacting functional elements: debug bus unit (DBU), debug command unit (DCU), debug instruction Unit (DIU), debug inject/extract unit (DJU), and a debug flow unit (DFU). The DBU provides circuitry for buffering data received from the signal processor and other functional elements within the debug port as well as accepting data from an external source. The DBU provides for off-chip connections. The DCU provides circuitry for decoding and executing debug commands received by the debug port. The DIU provides circuitry to insert one or more instructions with, or without, data into the instruction stream of the signal processor.

Abstract: The signal processor including a CPU 10 which selects a context register 16, the contents of which configure an address generator 20 and a data type converter 22. A narrow parameter from the CPU 10 produces a broad address for the generator 20 to pass to the memory 28. The converter 22 converts data between memory 28 format and CPU 10 format. A different context register 16 may be selected by each code line of software. The generator 20 preferably calculates a data element length which is the product of an odd number and a power of two, each number being specified in the content of the Context Register 16. Elements are clustered into groups, one group for each element length, and the groups are arranged in order of ascending element length. The index identifying the individual element of a group with a larger element length does not begin with zero (or one).