Patents by Inventor Keith M. Jackson

Keith M. Jackson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Ultra-thin gate dielectrics
    Patent number: 6808993
    Abstract: An in-situ ultra dilute ammonia nitridation process and apparatus of the following ultra-thin chemically tailored gate dielectrics: DCE/O2 (Trans 1,2-Dichloroethylene) based ultra-thin gate dielectric; Nitric Oxide (NO) based ultra-thin gate dielectric that has been re-oxidized via a DCE/O2 (Trans 1,2-Dichloroethylene) process; “dry-wet” DCE (Trans 1,2-Dichloroethylene)/O2-H2O/O2) based ultra-thin gate dielectric; and ultra dilute, less than 1E-7 moles NH3/mm2, nitridation of an ultra-thin gate dielectric. A vertical diffusion furnace (VDF) is provided to process the same. The ultra-thin chemically tailored gate dielectrics generated in a VDF with ultra-dilute NH3, below 1E-7 moles NH3/mm2, in-situ nitridation show a performance comparable or better to traditional ex-situ rapid thermal anneal (RTA) processing techniques for 90 nm CMOS technology.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: October 26, 2004
    Assignee: Intel Corporation
    Inventors: Christine M. Finnie, Pauline N. Jacob, Nick Lindert, Keith M. Jackson, Kirk Althoff, Jack Hwang, Jack Kavalieros, James R. Mueller
  • Ultra-thin gate dielectrics
    Publication number: 20040132316
    Abstract: An in-situ ultra dilute ammonia nitridation process and apparatus of the following ultra-thin chemically tailored gate dielectrics: DCE/O2 (Trans 1,2-Dichloroethylene) based ultra-thin gate dielectric; Nitric Oxide (NO) based ultra-thin gate dielectric that has been re-oxidized via a DCE/O2 (Trans 1,2-Dichloroethylene) process; “dry-wet” DCE (Trans 1,2-Dichloroethylene)/O2-H2O/O2) based ultra-thin gate dielectric; and ultra dilute, less than 1E-7 moles NH3/mm2, nitridation of an ultra-thin gate dielectric. A vertical diffusion furnace (VDF) is provided to process the same. The ultra-thin chemically tailored gate dielectrics generated in a VDF with ultra-dilute NH3, below 1E-7 moles NH3/mm2, in-situ nitridation show a performance comparable or better to traditional ex-situ rapid thermal anneal (RTA) processing techniques for 90 nm CMOS technology.
    Type: Application
    Filed: January 8, 2003
    Publication date: July 8, 2004
    Inventors: Christine M. Finnie, Pauline N. Jacob, Nick Lindert, Keith M. Jackson, Kirk Althoff, Jack Hwang, Jack Kavalieros, James R. Mueller
  • Tamper proof security measure in data writing to non-volatile memory
    Patent number: 5715431
    Abstract: A method of writing data to non-volatile memory such as electrically erasable programmable read only memory (EEPROM) in a smart card provides a write status region of EEPROM which is examined on each reset of the card. If the preceding write operation was unsuccessful, perhaps because of deliberate manipulation of the card, a recovery procedure is implemented. If recovery is successful, the card operation can be run. Otherwise the card is unusable.
    Type: Grant
    Filed: February 3, 1995
    Date of Patent: February 3, 1998
    Assignee: Mondex International Limited
    Inventors: David B. Everett, Keith M. Jackson, Ian Miller