Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: A microwave PIN diode having an increased intrinsic region volume for storing a charge. A semiconductor substrate has an N+ subcollector/cathode layer which encloses a region of the substrate. An N-skin formed over the interior of enclosed region. An Si layer is formed over the subcollector/cathode and N-skin to a thickness which defines the thickness for the intrinsic region of the diode. Implants are formed in the Si layer to permit contact with the subcollector/cathode layer. An anode is formed on the top of the Si layer. The total volume of the intrinsic region is increased by the N-skin which is positioned below the surface of the subcollector/cathode. The PIN diode may be formed as a lateral PIN diode thereby increasing the intrinsic region volume even further.

Abstract: The invention provides a PIN diode having a laterally extended I-region. The invention also provides a method of fabricating the inventive PIN diode compatible with modern RF technologies such as silicon-germanium BiCMOS processes.

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: The invention provides a PIN diode having a laterally extended I-region. The invention also provides a method of fabricating the inventive PIN diode compatible with modem RF technologies such as silicon-germanium BiCMOS processes.

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: A low noise, high frequency solid state diode is provided from a plurality of unit diode cells which are interconnected in parallel. Each of the unit diode cells forms an element of an array having rows and columns of unit diode cells. The diode cells include a base region of polysilicon, forming an anode, and an active cathode region which forms a diode junction with the anode. A plurality of overlapping subcollector regions interconnect the cathode regions, to provide a single, continuous collector for the diode arrays. The base region has a minimum perimeter to area ratio which reduces the resistance of each active diode region. A plurality of cathode contacts are connected to the subcollector through a respective reach region of highly doped semiconductor material. One or more metalization layers connect the cathode regions together, and the anodes of the base regions together. By controlling the size and shape of the base region of polysilicon, the series resistance of the resulting diode is minimized.

Abstract: A Conductor Insulator Semiconductor (CIS) heterojunction transistor. The CIS transistor is on silicon (Si) substrate. A layer of n type Si is deposited on the substrate. A trench is formed through the n type Si layer, and may extend slightly into the substrate. The trench is filled with an insulator, preferably SiO.sub.2. A layer of p type Si.sub.1-z Ge.sub.z (where z is the mole fraction of Ge and 0.1.ltoreq.z.ltoreq.0.9) is deposited on the n type Si layer. A p.sup.+ base contact region is defined in the p type Si.sub.1-z Ge.sub.z region above the oxide filled trench. A n type dopant is ion implanted into both the Si.sub.1-z Ge.sub.z and n Si layers and may extend slightly into the substrate, forming a collector region. A thin oxide layer is deposited on the Si.sub.1-z Ge.sub.z layer and a low work function metal such as Al, Mg, Mn, or Ti is selectively deposited on the thin oxide and to define an emitter. Alternatively, the emitter may be p.sup.+ polysilicon.

Abstract: A Conductor Insulator Semiconductor (CIS) heterojunction transistor. The CIS transistor is on silicon (Si) substrate. A layer of n type Si is deposited on the substrate. A trench is formed through the n type Si layer, and may extend slightly into the substrate. The trench is filled with an insulator, preferably SiO.sub.2. A layer of p type Si.sub.1-z Ge.sub.z (where z is the mole fraction of Ge and 0.1.ltoreq.z.ltoreq.0.9) is deposited on the n type Si layer. A p.sup.+ base contact region is defined in the p type Si.sub.1-z Ge.sub.z region above the oxide filled trench. A n type dopant is ion implanted into both the Si.sub.1-z Ge.sub.z and n Si layers and may extend slightly into the substrate, forming a collector region. A thin oxide layer is deposited on the Si.sub.1-z Ge.sub.z layer and a low work function metal such as Al, Mg, Mn, or Ti is selectively deposited on the thin oxide and to define an emitter. Alternatively, the emitter may be p.sup.+ polysilicon.