Abstract: A clamp circuit (10) for protecting a MOSFET (12) from destructive voltages and currents includes a clamping element (30), a current switch (27), a bond pad (23), a probe pad (25), and a resistor (21). When no external signal is applied to the probe pad (25), a FET (18) in the clamping element (30) is conductive. When the drain voltage of the MOSFET (12) rises above a clamping voltage of the clamping element (30), a current flows through the clamping element (30) and switches on the MOSFET (12). To ensure a safe operating area of the MOSFET (12), a voltage is applied to the probe pad (25) to turn off the FET (18), a breakdown voltage of the MOSFET (12) measured from the bond pad (23) is compared with the clamp voltage, and circuit die with the breakdown voltage less than the clamp voltage are discarded.

Abstract: A clamp circuit (50) for protecting a MOSFET (52) from destructive voltages includes a clamping element (56), a Zener diode (64), two current mirrors (66 and 62), a current switch (58), a reference current source (68), and a voltage detector (72). When a drain voltage of the MOSFET (52) rises above a clamping voltage of the clamp circuit (50), a clamping current exceeding a current in the current switch (58) flows through the clamping element (56) and activates the MOSFET (52). During the activation, the two current mirrors (66 and 62) generate an output current exceeding a reference current in the reference current source (68) and raise a voltage at an input terminal of the voltage detector (72). The voltage detector (72) generates a signal indicating the activation of the clamp circuit (50), thereby indicating that the clamp circuit (50) and its inductive load (74) are intact.

Abstract: A single ended input comparator circuit having an input inverter stage and a voltage reference circuit is provided. The voltage reference circuit modulates the voltage appearing across the inverter stage thereby varying the switching threshold voltage level of the inverter stage and providing hysteresis for the comparator circuit. Further, by appropriately choosing the widths and lengths of the transistors used in the inverter stage and the voltage reference circuit, a zero temperature coefficient for the comparator circuit is achieved.

Abstract: An integrated circuit power timer having a power field effect transistor and a versatile timing circuit all on one integrated circuit is provided. The integrated circuit has built in thermal and current limit protection and provides a fault indicator in case of an over current or an over temperature condition.

Abstract: A speed control circuit made by using CMOS processes is capable of handling high voltage and high current loads. The output of the speed control circuit is provided by a power field effect transistor. Current sensing means are provided to generate a fault signal in case an over current condition occurs. The junction temperature of the power field effect transistor is also monitored to provide an over temperature condition if the temperature of the junction of the power field effect transistor exceeds a predetermined value. A ramping generator is used to set a latch which controls the operation of the power field effect transistor. A speed control signal is compared against the ramping signal provided by the ramp generator and resets the latch in order to provide speed control.