Patents by Inventor Keith P. Donegan

Keith P. Donegan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnect formation with chamferless via, and related interconnect
    Patent number: 10566231
    Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Martin J. O'Toole, Christopher J. Penny, Jae O. Choo, Adam L. da Silva, Craig Child, Terry A. Spooner, Hsueh-Chung Chen, Brendan O'Brien, Keith P. Donegan
  • Substrate structure with spatial arrangement configured for coupling of surface plasmons to incident light
    Patent number: 10510675
    Abstract: Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Somnath Ghosh, Eswar Ramanathan, Qanit Takmeel, Ming He, Jeric Sarad, Ashwini Chandrashekar, Colin Bombardier, Anbu Selvam KM Mahalingam, Keith P. Donegan, Prakash Periasamy
  • INTERCONNECT FORMATION WITH CHAMFERLESS VIA, AND RELATED INTERCONNECT
    Publication number: 20190333805
    Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Martin J. O'Toole, Christopher J. Penny, Jae O. Choo, Adam L. da Silva, Craig Child, Terry A. Spooner, Hsueh-Chung Chen, Brendan O'Brien, Keith P. Donegan
  • SUBSTRATE STRUCTURE WITH SPATIAL ARRANGEMENT CONFIGURED FOR COUPLING OF SURFACE PLASMONS TO INCIDENT LIGHT
    Publication number: 20190244911
    Abstract: Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.
    Type: Application
    Filed: February 5, 2018
    Publication date: August 8, 2019
    Inventors: Somnath Ghosh, Eswar Ramanathan, Qanit Takmeel, Ming He, Jeric Sarad, Ashwini Chandrashekar, Colin Bombardier, Anbu Selvam KM Mahalingam, Keith P. Donegan, Prakash Periasamy