Abstract: In one embodiment, a first dielectric layer (32) that overlies a fuse (16) and a bonding pad (30) is etched with a first etch process. This first etch process exposes a portion (40) of a second dielectric layer (20) that underlies the first dielectric layer (32) and overlies the fuse (16). In addition, the first etch process also forms a bond pad opening (38) that exposes a portion (42) of an anti-reflective layer (28) that forms a portion of the bonding pad (30). A second etch process is then used to etch the exposed portion (42) of the anti-reflective layer (28) and the exposed portion (40) of the second dielectric layer (20) at substantially the same rate to form a fuse window (45) overlying the fuse (16). The second etch process prevents over etching of the second dielectric layer (20), and thus exposure of the underlying fuse (16).

Abstract: A semiconductor device fabrication method in which a conductive interconnect is formed over a semiconductor substrate. First and second dielectric films are formed over the interconnect. A first patterning layer is formed over the second dielectric. A via opening is then formed in the first patterning layer and a second patterning layer is formed over the first patterning layer. A trench opening is defined in the second patterning layer. A first portion of the second dielectric film exposed by the trench opening is removed to define a via pattern. A portion of the first patterning layer exposed by the second patterning layer is then removed to expose a second portion of the second dielectric film, which is then removed to define a trench portion of a dual inlaid opening in the second dielectric. A portion of the first dielectric film defined by the via pattern is then removed to expose the conductive region.

Abstract: An opening (24) is formed in a substrate (20). A first layer (30) is formed over the substrate (20) and the feature opening (24). A second layer (40) is formed over the first layer (30) and then the second layer is removed until exposing portions (50) of the first layer (30). The exposed portions (50) of the first layer (30) are then optionally removed using remaining portions (52) of the second layer (40) as a patterning mask to form a cavity (60) in the first layer (30). The remaining portions of the second layer (52) are then removed and the first layer (30) is polished to form a semiconductor device structure (80). In one embodiment, the first layer is dielectric layer, and in an alternative embodiment, the first layer is a conductive layer.