Abstract: A decision directed flicker noise canceller for reducing flicker noise in a modulated input signal according to an embodiment of the present invention includes a decision circuit, a conversion circuit, first and second adders and a filter. The decision circuit provides signal decisions based on the input signal. The conversion circuit provides selected signal values based on the signal decisions. The first adder subtracts the selected signal values from signals based on the input signal to provide a flicker noise estimate. The filter receives and filters the flicker noise estimate and the second adder subtracts the filtered flicker noise estimate from the input signal and provides a corrected input signal. In a feedback configuration, the second adder is located in a feedback position before the decision circuit in the signal processing path. In a feed-forward configuration, the second adder is located in a feed-forward position after the decision circuit.

Abstract: A decision directed flicker noise canceller for reducing flicker noise in a modulated input signal according to an embodiment of the present invention includes a decision circuit, a conversion circuit, first and second adders and a filter. The decision circuit provides signal decisions based on the input signal. The conversion circuit provides selected signal values based on the signal decisions. The first adder subtracts the selected signal values from signals based on the input signal to provide a flicker noise estimate. The filter receives and filters the flicker noise estimate and the second adder subtracts the filtered flicker noise estimate from the input signal and provides a corrected input signal. In a feedback configuration, the second adder is located in a feedback position before the decision circuit in the signal processing path. In a feed-forward configuration, the second adder is located in a feed-forward position after the decision circuit.

Abstract: A decision directed flicker noise canceller for reducing flicker noise in a modulated input signal according to an embodiment of the present invention includes a decision circuit, a conversion circuit, first and second adders and a filter. The decision circuit provides signal decisions based on the input signal. The conversion circuit provides selected signal values based on the signal decisions. The first adder subtracts the selected signal values from signals based on the input signal to provide a flicker noise estimate. The filter receives and filters the flicker noise estimate and the second adder subtracts the filtered flicker noise estimate from the input signal and provides a corrected input signal. In a feedback configuration, the second adder is located in a feedback position before the decision circuit in the signal processing path. In a feed-forward configuration, the second adder is located in a feed-forward position after the decision circuit.

Abstract: A method of controlling operation of a wireless device configured in a zero intermediate frequency architecture including a DC loop and a gain loop. The method includes processing energy in a wireless medium to generate a corresponding receive signal, monitoring the receive signal via a predetermined measurement window, detecting a changed condition in the channel, holding the gain feedback control loop at a constant gain level, and operating the DC loop in an attempt to search a stable DC value for the receive signal while the gain loop is held constant. A first case is DC saturation, where the gain is held constant until DC is controlled. A second case is clear channel assessment, where a prior stored gain setting is applied to the gain loop after detecting the end of the packet. A third case is preparation for receiving an expected acknowledgement packet after transmitting a packet, where again a prior stored gain setting is applied to the gain loop and DC is searched.

Abstract: A wireless receiver including a baseband processor that includes a compensation system that selectively includes an equalizer and a CMF that process received digital samples from a wireless medium, and a CIR estimator that calculates filter weights based on the samples. A memory stores default filter weights and select logic selects between calculated filter weights of the CIR estimator and the default filter weights from the memory. An SNR estimator receives the samples and provides an SNR metric and a multipath estimator receives the calculated filter weights and provides a multipath metric. The decision logic determines an operating point of the receiver using the SNR and multipath metrics, makes a decision based on the determined operating point according to a predetermined packet error rate (PER) performance mapping, and controls the select logic to select between the default and calculated filter weights and selectively enables the equalizer.

Abstract: A receiver including an analog Barker detector including digital processing logic, a radio and an analog-to-digital converter (ADC). The digital processing logic has a receive signal input for processing digital baseband signals and a power activation input for receiving a detection signal. The radio receives and converts radio frequency (RF) signals into analog baseband signals, and includes a Barker matched filter coupled to receive the analog baseband signals, an envelope detector, a peak detector, and a counter circuit. The counter circuit detects Barker signals and provides the detection signal for powering up the digital processing logic. The digital processing logic is powered down between signal acquisitions to conserve power and powers up in response to the detection signal. The ADC may also be powered up and down in a similar manner to conserve additional power.

Abstract: A decision directed flicker noise canceller for reducing flicker noise in a modulated input signal according to an embodiment of the present invention includes a decision circuit, a conversion circuit, first and second adders and a filter. The decision circuit provides signal decisions based on the input signal. The conversion circuit provides selected signal values based on the signal decisions. The first adder subtracts the selected signal values from signals based on the input signal to provide a flicker noise estimate. The filter receives and filters the flicker noise estimate and the second adder subtracts the filtered flicker noise estimate from the input signal and provides a corrected input signal. In a feedback configuration, the second adder is located in a feedback position before the decision circuit in the signal processing path. In a feed-forward configuration, the second adder is located in a feed-forward position after the decision circuit.

Abstract: An RF device including a control loop for maximizing output power for each of several data rates or constellation types. The RF device includes a power detector, a power amplifier and a MAC that includes input and output adjust circuits. A power level value is generated from measured output power. The MAC compares an adjusted power level value with a set point value and generates an error value. The MAC adjusts a power control value based on the error value for controlling the gain of the power amplifier. The MAC uses a data rate signal indicative of a selected constellation type or data rate. The input adjust circuit stores one or more input adjustment values selected by the data select signal for adjusting the power level value. The output adjust circuit stores one or more output adjustment values selected by the data select signal for adjusting the power control value.

Abstract: A calibrated DC compensation system for a wireless communication device configured in a zero intermediate frequency (ZIF) architecture. The device includes a ZIF transceiver and a baseband processor, which further includes a calibrator that periodically performs a calibration procedure. The baseband processor includes gain control logic, DC control logic, a gain converter and the calibrator. The gain converter converts gain between the gain control logic and the DC control logic. The calibrator programs the gain converter with values determined during the calibration procedure. The gain converter may be a lookup table that stores gain conversion values based on measured gain of a baseband gain amplifier of the ZIF transceiver. The gain control logic may further include a gain adjust limiter that limits change of a gain adjust signal during operation based on a maximum limit or on one or more gain change limits.

Abstract: A threshold detector for detecting synchronization signals at correlator output during packet acquisition. An RF receiver converts RF signals into baseband signals. A matched filter correlator correlates samples of the baseband signals with predetermined synchronization signals, such as long sync symbols, and provides corresponding correlation samples. A long-term integrator integrates a first predetermined number of the correlation samples to provide a long term moving average and a short term integrator integrates a second predetermined number of the correlation samples to provide a short term moving average signal. The short term moving average signal is based on channel delay spread and the long term moving average tracks channel noise. A multiplier multiplies the long term moving average signal by a scale factor to generate a dynamic threshold. A detector detects a crossover between the short term moving average and the dynamic threshold to estimate timing of received synchronization signals.

Abstract: A channel estimator for use with the wireless digital data receiver facilitates processing of a preamble symbol sequence received over a multipath communication channel to enable the impulse response of the channel to be rapidly estimated, and thereby set the parameters of the receiver's decision feedback equalizer. During the preamble dwell interval, selected estimates of one or more received preamble symbols within a plurality of successive data symbols are repeated, in order to generate a longer sequence of preamble symbol estimates. The receiver's processor then employs this longer sequence of data symbol values, to solve an associated set of linear equations for estimating the multipath channel's impulse response.

Abstract: A threshold detector for detecting synchronization signals at correlator output during packet acquisition. An RF receiver converts RF signals into baseband signals. A matched filter correlator correlates samples of the baseband signals with predetermined synchronization signals, such as long sync symbols, and provides corresponding correlation samples. A long-term integrator integrates a first predetermined number of the correlation samples to provide a long term moving average and a short term integrator integrates a second predetermined number of the correlation samples to provide a short term moving average signal. The short term moving average signal is based on channel delay spread and the long term moving average tracks channel noise. A multiplier multiplies the long term moving average signal by a scale factor to generate a dynamic threshold. A detector detects a crossover between the short term moving average and the dynamic threshold to estimate timing of received synchronization signals.

Abstract: A rapid acquisition gain control system for use in a wireless communication device having an RF input and a receive signal path including RF and baseband portions. The system includes two or more dual-state gain elements, two or more power detectors and control logic. The gain elements are sequentially coupled in the receive signal path of the wireless device and collectively have multiple combined gain states. Each combined gain state corresponds to one of several gain range segments of a predetermined dynamic range. Each power detector is coupled to detect an output power level associated with one of the gain elements. The control logic changes the combined gain state of the gain elements if a change of power level of energy processed in the receive signal path exceeds a predetermined threshold and a different combined gain state is indicated by the power detectors.

Abstract: An RF device including a control loop for maximizing output power for each of several data rates or constellation types. The RF device includes a power detector, a power amplifier and a MAC that includes input and output adjust circuits. A power level value is generated from measured output power. The MAC compares an adjusted power level value with a set point value and generates an error value. The MAC adjusts a power control value based on the error value for controlling the gain of the power amplifier. The MAC uses a data rate signal indicative of a selected constellation type or data rate. The input adjust circuit stores one or more input adjustment values selected by the data select signal for adjusting the power level value. The output adjust circuit stores one or more output adjustment values selected by the data select signal for adjusting the power control value.

Abstract: A method and system for determining gain taps values for a pre-compensation transmit frequency domain equalizer of a wireless transmitter. Each tap of the equalizer scales a zone and each zone includes at least one sub-carrier. To reduce the number of taps, one or more zones may incorporate more than one sub-carrier. The method includes providing test information for processing by the transmitter, measuring sub-carrier magnitudes generated by the transmitter, normalizing the measured sub-carrier magnitudes, determining an average power value of the normalized sub-carrier magnitudes within each sub-carrier zone, and finding a gain value for each sub-carrier zone so that when multiplied by the average power value of that sub-carrier zone comes closest to a predetermined target value. The normalizing, determining and finding may be repeated for multiple target values to generate a multiple arrays of gain values, where one array that is closest to achieving a unity power gain is selected.

Abstract: A wireless communication device including a radio frequency (RF) circuit, a ZIF transceiver and a baseband processor. The ZIF transceiver includes an RF mixer circuit that converts the RF signal to a baseband input signal, a summing junction that subtracts a DC offset from the baseband input signal to provide an adjusted baseband input signal, and a baseband amplifier that receives the adjusted baseband input signal and that asserts an amplified input signal based on a gain adjust signal. The baseband processor includes gain control logic, DC control logic and a gain interface. The gain control logic receives the amplified input signal, estimates input signal power and asserts the gain adjust signal in an attempt to keep the input signal power at a target power level. The DC control logic estimates an amount of DC in the amplified input signal and provides the DC offset in an attempt to reduce DC in the amplified input signal.

Abstract: A wireless receiver including a baseband processor that includes a compensation system that selectively includes an equalizer and a CMF that process received digital samples from a wireless medium, and a CIR estimator that calculates filter weights based on the samples. A memory stores default filter weights and select logic selects between calculated filter weights of the CIR estimator and the default filter weights from the memory. An SNR estimator receives the samples and provides an SNR metric and a multipath estimator receives the calculated filter weights and provides a multipath metric. The decision logic determines an operating point of the receiver using the SNR and multipath metrics, makes a decision based on the determined operating point according to a predetermined packet error rate (PER) performance mapping, and controls the select logic to select between the default and calculated filter weights and selectively enables the equalizer.

Abstract: A method of controlling operation of a wireless device configured in a zero intermediate frequency architecture including a DC loop and a gain loop. The method includes processing energy in a wireless medium to generate a corresponding receive signal, monitoring the receive signal via a predetermined measurement window, detecting a changed condition in the channel, holding the gain feedback control loop at a constant gain level, and operating the DC loop in an attempt to search a stable DC value for the receive signal while the gain loop is held constant. A first case is DC saturation, where the gain is held constant until DC is controlled. A second case is clear channel assessment, where a prior stored gain setting is applied to the gain loop after detecting the end of the packet. A third case is preparation for receiving an expected acknowledgement packet after transmitting a packet, where again a prior stored gain setting is applied to the gain loop and DC is searched.

Abstract: An apparatus for blind signal separation and equalization of PAM signals on a full duplex transmission line is capable of successfully extracting and recovering the respective signalling components of a full-duplex wireline digital data link without having to disturb the link during its use (e.g. as by interrupting service to sever the link in order to install a line coupling device, such as a modem or attenuator pad to signal monitoring equipment) and without having to generate PN or other training sequences. A full-duplex wireline bridge device comprises a signal characteristic monitoring device that is capable of monitoring the link and providing respective output signals representative of the respective unidirectional signal components being transmitted simultaneously in opposite directions along the link.

Abstract: A method of controlling operation of a wireless device configured in a zero intermediate frequency architecture including a DC loop and a gain loop. The method includes processing energy in a wireless medium to generate a corresponding receive signal, monitoring the receive signal via a predetermined measurement window, detecting a changed condition in the channel, holding the gain feedback control loop at a constant gain level, and operating the DC loop in an attempt to search a stable DC value for the receive signal while the gain loop is held constant. A first case is DC saturation, where the gain is held constant until DC is controlled. A second case is clear channel assessment, where a prior stored gain setting is applied to the gain loop after detecting the end of the packet. A third case is preparation for receiving an expected acknowledgement packet after transmitting a packet, where again a prior stored gain setting is applied to the gain loop and DC is searched.