Patents by Inventor Keith R. Cook

Keith R. Cook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10128142
    Abstract: A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars of the device wafer. The carrier wafer and the device wafer are fusion bonded together and back side processing effected on the device wafer. The device wafer may be released from the carrier wafer by one or more of mechanically cleaving, thermally cleaving, and mechanically separating. Methods of forming the semiconductor structure including the carrier wafer and the device wafer are disclosed.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: November 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sharon N. Farrens, Keith R. Cook
  • Publication number: 20170011948
    Abstract: A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars of the device wafer. The carrier wafer and the device wafer are fusion bonded together and back side processing effected on the device wafer. The device wafer may be released from the carrier wafer by one or more of mechanically cleaving, thermally cleaving, and mechanically separating. Methods of forming the semiconductor structure including the carrier wafer and the device wafer are disclosed.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 12, 2017
    Inventors: Sharon N. Farrens, Keith R. Cook
  • Patent number: 9472518
    Abstract: A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars of the device wafer. The carrier wafer and the device wafer are fusion bonded together and back side processing effected on the device wafer. The device wafer may be released from the carrier wafer by one or more of mechanically cleaving, thermally cleaving, and mechanically separating. Methods of forming the semiconductor structure including the carrier wafer and the device wafer are disclosed.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: October 18, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Sharon N. Farrens, Keith R. Cook
  • Publication number: 20150287687
    Abstract: A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars of the device wafer. The carrier wafer and the device wafer are fusion bonded together and back side processing effected on the device wafer. The device wafer may be released from the carrier wafer by one or more of mechanically cleaving, thermally cleaving, and mechanically separating. Methods of forming the semiconductor structure including the carrier wafer and the device wafer are disclosed.
    Type: Application
    Filed: April 4, 2014
    Publication date: October 8, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Sharon N. Farrens, Keith R. Cook
  • Patent number: 8349699
    Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: January 8, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Robert D. Patraw, Martin Ceredig Roberts, Keith R. Cook
  • Publication number: 20110300689
    Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material.
    Type: Application
    Filed: August 16, 2011
    Publication date: December 8, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Robert D. Patraw, M. Ceredig Roberts, Keith R. Cook
  • Patent number: 8012847
    Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: September 6, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Robert D. Patraw, M. Ceredig Roberts, Keith R. Cook
  • Patent number: 7939948
    Abstract: Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: May 10, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Mark E. Tuttle, Keith R. Cook
  • Publication number: 20090179330
    Abstract: Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.
    Type: Application
    Filed: March 23, 2009
    Publication date: July 16, 2009
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Mark E. Tuttle, Keith R. Cook
  • Patent number: 7528064
    Abstract: Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: May 5, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Mark E. Tuttle, Keith R. Cook
  • Patent number: 7387940
    Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: June 17, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Robert D. Patraw, M. Ceredig Roberts, Keith R. Cook
  • Patent number: 7282433
    Abstract: Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Mark E. Tuttle, Keith R. Cook
  • Patent number: 5616182
    Abstract: A wiping system and method for wiping a windshield is shown. The wiping system comprises frictional material or a wiper material which is applied directly to either a wiper blade or a windshield in at least one reversal area on the windshield where the wiping blade is driven from a first direction to a second direction which is generally opposite that of the first direction. The wiper material is coated or integrally formed as part of the windshield in the reversal areas to facilitate increasing the friction between an edge of the wiper blade and a surface of the windshield which, in turn, facilitates causing the blade to flip from a first wipe side to a second wipe side, thereby reducing or eliminating "chisel chatter" problems of the past.
    Type: Grant
    Filed: December 4, 1995
    Date of Patent: April 1, 1997
    Assignee: ITT Automotive Electrical Systems, Inc.
    Inventor: Keith R. Cook
  • Patent number: 4850466
    Abstract: A power door lock actuator includes a one piece molded and centrifugally expandable brake ring that is held on a drive ring to a motor shaft within a lock lift arm driving cup that is freely pivoted to the shaft. A camming member on the drive ring fits within the brake ring so as to retain it to the shaft, to maintain it in a ready position spaced from the cup when stationary, and so as to jam it into the wall of the cup when turning.
    Type: Grant
    Filed: May 19, 1988
    Date of Patent: July 25, 1989
    Assignee: General Motors Corporation
    Inventors: Deno J. Rogakos, Lynn M. Johnston, Keith R. Cook
  • Patent number: 4633153
    Abstract: Motor control apparatus is disclosed for a motor driven vehicle power window mechanism including a flexible drive element, such as a drive tape, adapted to drive the window in a predetermined direction by being placed in tension by the motor. The tension of the flexible drive element is relieved by automatically reversing motor direction for a short time when the window reaches the desired position. The reverse motor rotation is accurately controlled to an amount sufficient to relieve drive tension but insufficient to produce unwanted reverse movement of the window by detecting the pulses of the armature ripple current as the successive commutator bars pass the brushes during reverse motor rotation, integrating these pulses and stopping the reverse motor operation when the integrated value reaches a predetermined reference.
    Type: Grant
    Filed: February 24, 1986
    Date of Patent: December 30, 1986
    Assignee: General Motors Corporation
    Inventors: Dennis P. Thornton, John S. Maceross, Jeff A. Foust, Keith R. Cook
  • Patent number: 4398704
    Abstract: Pneumatic suspension system for automotive application in which sprung and unsprung masses are supported by variable volume air spring units and incorporating compressor and exhaust valve devices for supplying an exhausting pressurized air from the units to adjust the height between the masses. A Hall effect device effective across a pressure boundary senses the position of a magnet movable within one of the air spring units and reflects relative movement of the sprung and unsprung masses to effect control of the supply and exhaust of air from the units. By axial movement of the Hall device, dead band width can be established to accommodate normal ride motions between sprung and unsprung components. By rotating the Hall device at any axial position, the vehicle bumper height can be selectively increased or decreased.
    Type: Grant
    Filed: January 26, 1982
    Date of Patent: August 16, 1983
    Assignee: General Motors Corporation
    Inventors: Harry C. Buchanan, Jr., Donald E. Graham, Keith R. Cook, George T. Claude
  • Patent number: 4355270
    Abstract: A motor reversing control circuit for a motor vehicle windshield wiper has a motor driven cam with a first lobe defining a park position for the wiper and a second lobe defining, in relation to the first, a wipe angle. A park switch is actuated by either lobe to reverse the output of a flip-flop which controls motor direction. The motor is activated in response to one or more of (a) a main switch, (b) the unactuated park switch and (c) the flip-flop output signalling wiper movement toward the park position. An optional timer effective to delay the motor activation in response to the main switch provides a pause in the park position.
    Type: Grant
    Filed: December 2, 1981
    Date of Patent: October 19, 1982
    Assignee: General Motors Corporation
    Inventors: Keith R. Cook, John E. Pozenel, Donald E. Graham