Patents by Inventor Keith Rieken
Keith Rieken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8938250Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: GrantFiled: July 25, 2013Date of Patent: January 20, 2015Assignee: Intel Mobible Communications GmbHInventors: Song Chen, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Publication number: 20140242321Abstract: The disclosure provides methods and materials for preparing bridging films. In one aspect, the bridging films are non-porous and are suitable for protecting adjacent porous films. For example, the bridging films contact a porous film and protect the porous film from transfer of gases and/or liquids into the pores of the porous film. In another example, bridging films protect the porous film from abrasion.Type: ApplicationFiled: May 2, 2014Publication date: August 28, 2014Applicant: Svana Nanotechnologies, Inc.Inventors: Siglinde Schmid, Melissa Fardy, J. Wallace Parce, Keith Rieken, Benjamin Wang, Kevin Krogman
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Publication number: 20130346726Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: ApplicationFiled: July 25, 2013Publication date: December 26, 2013Applicant: Intel Mobile Communications GmbHInventors: Song CHEN, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Patent number: 8526965Abstract: A wireless communication base station comprising a plurality of application specific instruction set processors (ASISPs) configured to support one or more processes hosted by the base station, and to track process state information associated with each of the processes; and a memory configured to store the tracked process state information, and when an ASISP of the plurality of ASISPs is reallocated from a first process to a second process, the respective ASISP is configured to retrieve from the memory process state information for the second process.Type: GrantFiled: June 22, 2012Date of Patent: September 3, 2013Assignee: Intel Mobile Communications GmbHInventors: Song Chen, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Publication number: 20120272042Abstract: A wireless communication base station comprising a plurality of application specific instruction set processors (ASISPs) configured to support one or more processes hosted by the base station, and to track process state information associated with each of the processes; and a memory configured to store the tracked process state information, and when an ASISP of the plurality of ASISPs is reallocated from a first process to a second process, the respective ASISP is configured to retrieve from the memory process state information for the second process.Type: ApplicationFiled: June 22, 2012Publication date: October 25, 2012Inventors: Song CHEN, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Patent number: 8244270Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: GrantFiled: July 29, 2011Date of Patent: August 14, 2012Assignee: Intel Mobile Communications GmbHInventors: Song Chen, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Patent number: 8151270Abstract: A method for designing a time-sliced and multi-threaded architecture comprises the steps of conducting a thorough analysis of a range of applications and building a specific processor to accommodate the range of applications. In one embodiment, the thorough analysis includes extracting real time aspects from each application, determining optimal granularity in the architecture based on the real time aspects of each application, and adjusting the optimal granularity based on acceptable context switching overhead.Type: GrantFiled: August 20, 2007Date of Patent: April 3, 2012Assignee: Infineon Technologies AGInventors: Keith Rieken, Joel D. Medlock, David M. Holmes
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Publication number: 20110314257Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: ApplicationFiled: July 29, 2011Publication date: December 22, 2011Inventors: Song CHEN, Paul L. CHOU, Christopher C. WOODTHORPE, Venugopal BALASUBRAMONIAN, Keith RIEKEN
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Patent number: 8014786Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: GrantFiled: August 20, 2007Date of Patent: September 6, 2011Assignee: Infineon Technologies AGInventors: Song Chen, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Patent number: 7616680Abstract: A method for processing data in a spread spectrum system, including decimating a data rate of received spread spectrum data by a decimation factor to a decimated rate; storing the received spread spectrum data into a memory at the decimated rate; interpolating the decimated rate by an interpolation factor to an interpolated rate; and reading the received spread spectrum data from the memory at the interpolated rate.Type: GrantFiled: June 5, 2006Date of Patent: November 10, 2009Assignee: Infineon Technologies AGInventors: Joel D. Medlock, Keith Rieken, David M. Holmes
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Patent number: 7606576Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: GrantFiled: July 24, 2001Date of Patent: October 20, 2009Assignee: Infineon Technologies AGInventors: Song Chen, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Patent number: 7536691Abstract: An architecture and method for dynamic resource allocation and scheduling in a communication device is disclosed herein. The method of controlling hardware resources in a communication device having a processor, a computer readable memory, and at least one hardware resource coupled to each other includes several steps. The first step locates a memory address in the computer readable memory that is associated with a first hardware resource. In the next step, control information associated with the first memory address is transmitted to the first hardware resource for it to be operated. In the last step, a pointer associated with the first address that locates a subsequent address for a subsequent hardware resource, is read.Type: GrantFiled: August 9, 2001Date of Patent: May 19, 2009Assignee: Infineon Technologies AGInventors: Chakki Kavoori, Keith Rieken, David M. Holmes
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Patent number: 7512951Abstract: A method for designing a time-sliced and multi-threaded architecture comprises the steps of conducting a thorough analysis of a range of applications and building a specific processor to accommodate the range of applications. In one embodiment, the thorough analysis includes extracting real time aspects from each application, determining optimal granularity in the architecture based on the real time aspects of each application, and adjusting the optimal granularity based on acceptable context switching overhead.Type: GrantFiled: July 31, 2001Date of Patent: March 31, 2009Assignee: Infineon Technologies AGInventors: Keith Rieken, Joel D. Medlock, David M. Holmes
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Publication number: 20080092141Abstract: A method for designing a time-sliced and multi-threaded architecture comprises the steps of conducting a thorough analysis of a range of applications and building a specific processor to accommodate the range of applications. In one embodiment, the thorough analysis includes extracting real time aspects from each application, determining optimal granularity in the architecture based on the real time aspects of each application, and adjusting the optimal granularity based on acceptable context switching overhead.Type: ApplicationFiled: August 20, 2007Publication date: April 17, 2008Applicant: INFINEON TECHNOLOGIES AGInventors: Keith Rieken, Joel Medlock, David Holmes
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Publication number: 20080084850Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: ApplicationFiled: August 20, 2007Publication date: April 10, 2008Applicant: INFINEON TECHNOLOGIES AGInventors: Song Chen, Paul Chou, Christopher Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Publication number: 20060291542Abstract: An apparatus for reducing storage requirements and for allowing reuse of multiple rake fingers in a spread spectrum system includes a decimation circuit having an associated decimation factor, a memory coupled to the decimation circuit, and an interpolation circuit having an interpolation factor coupled to the memory. The decimation circuit decimates the sampling rate of received data to produce a decimated rate. The received data is stored in the memory at the decimated rate. The decimated rate is later increased by the interpolation circuit by the interpolation factor when the stored data is retrieved from the memory. The memory is a circular buffer or a single port RAM that is accessible by multiple rake fingers substantially simultaneously via selector circuits.Type: ApplicationFiled: June 5, 2006Publication date: December 28, 2006Applicant: INFINEON TECHNOLOGIES AGInventors: Joel Medlock, Keith Rieken, David Holmes
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Patent number: 7065128Abstract: An apparatus for reducing storage requirements and for allowing reuse of multiple rake fingers in a spread spectrum system includes a decimation circuit having an associated decimation factor, a memory coupled to the decimation circuit, and an interpolation circuit having an interpolation factor coupled to the memory. The decimation circuit decimates the sampling rate of received data to produce a decimated rate. The received data is stored in the memory at the decimated rate. The decimated rate is later increased by the interpolation circuit by the interpolation factor when the stored data is retrieved from the memory. The memory is a circular buffer or a single port RAM that is accessible by multiple rake fingers substantially simultaneously via selector circuits.Type: GrantFiled: July 31, 2001Date of Patent: June 20, 2006Assignee: Infineon Technologies AGInventors: Joel D. Medlock, Keith Rieken, David M. Holmes
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Publication number: 20060039317Abstract: An apparatus for digitally processing signals within wireless communications base-stations which includes a channel pooling signal processor and a digital signal processor. The channel pooling signal processor includes a plurality of computation units typically realized in a heterogeneous multiprocessing architecture, a test interface for testing the function of the plurality of the computation units, a general-purpose microprocessor for managing the dataflow into and out of the channel pooling signal processor as well as effecting the control and configuration of the computation units, and an interconnect mechanism for connecting the plurality of computation units to the input, output, test interface, and the general-purpose microprocessor.Type: ApplicationFiled: August 9, 2005Publication date: February 23, 2006Applicant: Infineon Technologies AGInventors: Ravi Subramanian, Keith Rieken, Uma Jha, Joel Medlock, Christopher Woodthorpe
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Patent number: 7003015Abstract: This invention provides a configurable multi-dwell search engine for performing automated efficient searches of a known code sequence space. Inputs from a multi-dwell table and a finger control table are multiplexed by a first multiplexer. Output from the first multiplexer is used to generate a threshold comparison signal. The generated threshold comparison signal, the current dwell state signal and inputs from a next dwell look-up table are multiplexed by a second multiplexer. The second multiplexer outputs a hard hit signal and a offset control signal.Type: GrantFiled: July 31, 2001Date of Patent: February 21, 2006Assignee: Infineon Technologies AGInventor: Keith Rieken
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Patent number: 6967999Abstract: An apparatus for digitally processing signals within wireless communications base-stations which includes a channel pooling signal processor and a digital signal processor. The channel pooling signal processor includes a plurality of computation units typically realized in a heterogeneous multiprocessing architecture, a test interface for testing the function of the plurality of the computation units, a general-purpose microprocessor for managing the dataflow into and out of the channel pooling signal processor as well as effecting the control and configuration of the computation units, and an interconnect mechanism for connecting the plurality of computation units to the input, output, test interface, and the general-purpose microprocessor.Type: GrantFiled: December 29, 2000Date of Patent: November 22, 2005Assignee: Infineon Technologies AGInventors: Ravi Subramanian, Keith Rieken, Uma Jha, Joel D. Medlock, Christopher C. Woodthorpe