Abstract: A method of performing instruction marking in a computer processor architecture includes fetching instructions from a memory unit by a fetching unit in the computer processor architecture. Instruction groups for marking are determined. Fetched instructions are matched to instruction groups for marking. The fetched instructions are marked. Some of the marked instructions are selectively unmarked. The marked and unmarked instructions are forwarded to a queue of instructions for processing in the computer processor architecture.

Abstract: The present invention is directed to devices formed from three dimensional (3D) structures composed of wires, yarns of wires, or 3D printed structures. The devices of the present invention offer the potential for 3D structures with multiple properties optimized concurrently, using optimization within the 3D manufacturing constraints. The 3D structures of the present invention include multiple properties that are optimized for heat transfer applications. The present invention also includes the methods for optimization of the 3D woven lattices as well as methods of use of the 3D woven lattices in heat transfer applications.

Abstract: A heat pipe augmented passive solar space heating system modulates the temperature inside a building structure, particular during heating seasons when the ambient temperature is below levels customarily associated with adequate room comfort, and in some embodiments comprises a solar absorber, a heat pipe surrounding wholly or partially by insulation, the heat pipe having three main sections which are an evaporator at one end proximal to the solar absorber, a condenser at the other end proximal to an interior room being heated, and a rubber adiabatic section between those. Additional aspects such as a mechanical valve in the adiabatic section are disclosed to limit unwanted thermal gains when cooling is needed because the ambient temperatures already exceed room comfort.

Abstract: A heat pipe augmented passive solar space heating system modulates the temperature inside a building structure, particular during heating seasons when the ambient temperature is below levels customarily associated with adequate room comfort, and in some embodiments comprises a solar absorber, a heat pipe surrounding wholly or partially by insulation, the heat pipe having three main sections which are an evaporator at one end proximal to the solar absorber, a condenser at the other end proximal to an interior room being heated, and a rubber adiabatic section between those. Additional aspects such as a mechanical valve in the adiabatic section are disclosed to limit unwanted thermal gains when cooling is needed because the ambient temperatures already exceed room comfort.

Abstract: The present invention is directed to devices formed from three dimensional (3D) structures composed of wires, yarns of wires, or 3D printed structures. The devices of the present invention offer the potential for 3D structures with multiple properties optimized concurrently, using optimization within the 3D manufacturing constraints. The 3D structures of the present invention include multiple properties that are optimized for heat transfer applications. The present invention also includes the methods for optimization of the 3D woven lattices as well as methods of use of the 3D woven lattices in heat transfer applications.

Abstract: An adaptive crash structure for a vehicle includes a deformation element arranged in a region of a wheel housing of the vehicle, and an interruption system, wherein the deformation element and the interruption system are constructed so as to be able to change from a deactivated state to an activated state, wherein in the deactivated state the deformation element permits movement of a wheel housed in the wheel housing, and wherein in the activated state the deformation element causes the wheel to assume a predetermined position and the interruption system prevents a change of the position of the wheel to be transmitted to a steering wheel.

Abstract: An ultrasound probe includes a housing having an interior chamber formed therein. The ultrasound probe also includes an electronics assembly provided in the housing, the electronics assembly converting acoustic energy to electrical signals, and a tamper indicating substance applied to the ultrasound probe, the tamper indicating substance adapted to provide a visual indication when the ultrasound probe has been tampered with. A system including the ultrasound probe and a method of fabricating the ultrasound probe are also provided.

Abstract: A method and apparatus for controlling program instruction completion timing for processor verification provides, alternatively or in combination, an improved simulation technique and/or processor in which resource allocation as well as other performance-specific scenarios can be stressed over typical operating conditions by controlling the completion timing of one or more program instructions. A high-level program controlling simulation of a VHDL model of a processor can simulate extension of the completion time of a predetermined instruction in order to hold the instruction in the execution and completion queues, placing an effective hold on the resources allocated for the instruction. Alternatively, the VHDL model may include logic for controlling completion timing of the program instruction by using a processor clock cycle counter. Verification testing of actual processor hardware may be facilitated by including the counter and associated control logic within production or prototype processors.

Abstract: A method and apparatus for controlling program instruction completion timing for processor verification provides, alternatively or in combination, an improved simulation technique and/or processor in which resource allocation as well as other performance-specific scenarios can be stressed over typical operating conditions by controlling the completion timing of one or more program instructions. A high-level program controlling simulation of a VHDL model of a processor can simulate extension of the completion time of a predetermined instruction in order to hold the instruction in the execution and completion queues, placing an effective hold on the resources allocated for the instruction. Alternatively, the VHDL model may include logic for controlling completion timing of the program instruction by using a processor clock cycle counter. Verification testing of actual processor hardware may be facilitated by including the counter and associated control logic within production or prototype processors.

Abstract: A towel warmer comprising a cabinet enclosing a chamber with an opening, a door attached to the cabinet to close the opening, one or more coils heated by conducting hot water, the coils being positioned within the chamber opposite the opening, a resilient compressible support positioned on the door to compress cloth-like objects against the heated coils as the door is closed, and a latch to hold the door closed with force to maintain compression of the cloth-like objects against the heated coils.

Abstract: A hypodermic needle includes a hollow tube having an angled end with respect to a longitudinal axis of the tube, the end having an opening surrounded by an external peripheral rim. At least a portion of the external peripheral rim is beveled back at least 25%, to form an internal beveled surface.

Abstract: A towel warmer comprising a cabinet enclosing a chamber with an opening, a door attached to the cabinet to close the opening, one or more coils heated by conducting hot water, the coils being positioned within the chamber opposite the opening, a resilient compressible support positioned on the door to compress cloth-like objects against the heated coils as the door is closed, and a latch to hold the door closed with force to maintain compression of the cloth-like objects against the heated coils.

Abstract: A servo control system comprising, in a feedback loop, means for providing an error signal representing the difference between desired and actual conditions of a controlled system, and means responsive to said error signal to produce a control signal for the controlled system; the control system also comprising means for injecting a predetermined disturbance signal into the loop, and means responsive to a comparison of said disturbance signal and a loop response signal for varying gain in said loop.

Abstract: A multiplier circuit arrangement comprises two parallel paths for the same signal, one of the paths being associated with signal level adjusting means; and means responsive to inbalance of d.c. components including any in said parallel paths, the inbalance being in accordance with a d.c. signal in a third signal path, to produce a control signal for varying the signal level adjusting means to reduce the imbalance, so that a.c. components in said parallel paths will be unbalanced to an extent proportional to the d.c. signal in said third path.

Abstract: A multiplier circuit arrangement comprises two parallel paths for the same signal, one of the paths being associated with signal level adjusting means; and means responsive to imbalance of d.c. components including any in said parallel paths, th imbalance being in accordance with a d.c. signal in a third signal path, to produce a control signal for varying the signal level adjusting means to reduce the imbalance, so that a.c. components in said parallel paths will be unbalanced to an extent proportional to the d.c. signal in said third path. Such multipliers are particularly suited to resolving signals in a first set of axes into signals in a second set of axes where other signals are available which are combinable to give trigonometric functions required to translate between the first and second sets of axes.