Patents by Inventor Keith T. Kwietniak

Keith T. Kwietniak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7863189
    Abstract: Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with low defect density. In particular, methods are provided which enable fabrication of silicon carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghaven S. Basker, John Michael Cotte, Hariklia Deligianni, John Ulrich Knickerbocker, Keith T. Kwietniak
  • Patent number: 7678258
    Abstract: An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: March 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Keith T. Kwietniak, Peter S. Locke, Darryl D. Restaino, Soon-Cheon Seo, Philippe M. Vereecken, Erick G. Walton
  • Publication number: 20080164573
    Abstract: Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with, low defect density. In particular, methods are provided which enable fabrication of silicon, carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 10, 2008
    Inventors: Veeraraghaven S. Basker, John Michael Cotte, Hariklia Deligianni, John Ulrich Knickerbocker, Keith T. Kwietniak
  • Patent number: 7227265
    Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 ?m and via openings filled with electroplated copper than is substantially free of internal seams or voids.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: June 5, 2007
    Assignee: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, Steven H. Boettcher, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Christopher C. Parks, Soon-Cheon Seo, Andrew H. Simon, Erick G. Walton
  • Patent number: 7101784
    Abstract: The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: September 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Stephen E. Greco, Keith T. Kwietniak, Soon-Cheon Seo, Chih-Chao Yang, Yun-Yu Wang, Kwong H. Wong
  • Patent number: 6974531
    Abstract: A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: December 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Hariklia Deligianni, Wilma Jean Horkans, Keith T. Kwietniak, Michael Lane, Sandra G. Malhotra, Fenton Read McFeely, Conal Murray, Kenneth P. Rodbell, Philippe M. Vereecken
  • Patent number: 6921978
    Abstract: The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: July 26, 2005
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Stephen E. Greco, Keith T. Kwietniak, Soon-Cheon Seo, Chih-Chao Yang, Yun-Yu Wang, Kwong H. Wong
  • Publication number: 20040224494
    Abstract: The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features.
    Type: Application
    Filed: May 8, 2003
    Publication date: November 11, 2004
    Applicant: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Stephen E. Greco, Keith T. Kwietniak, Soon-Cheon Seo, Chih-Chao Yang, Yun-Yu Wang, Kwong H. Wong
  • Publication number: 20040178078
    Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &mgr;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 16, 2004
    Applicant: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, Steven H. Boettcher, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Christopher C. Parks, Soon-Cheon Seo, Andrew H. Simon, Erick G. Walton
  • Publication number: 20040178077
    Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &mgr;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 16, 2004
    Applicant: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, Steven H. Boettcher, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Christopher C. Parks, Soon-Cheon Seo, Andrew H. Simon, Erick G. Walton
  • Publication number: 20040077140
    Abstract: A uniformly thick oxide film on a substrate is formed by using an anodization apparatus which deposits a blanket precursor film on a surface of a substrate; provides electrical contact to the precursor film; moves the precursor film into contact with an electrolyte solution such that substantially all electrically conductive surfaces, e.g., pin contacts, the substrate edge and a backside of the substrate are electrically isolated from the electrolyte; ensures that the surface of the precursor film on the substrate is in direct contact with the electrolyte solution; and which applies an anodizing current and/or voltage between the precursor film and a counter electrode so as to compensate for a voltage drop resulting from the presence of the electrolyte.
    Type: Application
    Filed: October 16, 2002
    Publication date: April 22, 2004
    Inventors: Panayotis C. Andricacos, Roy Arthur Carruthers, Stephan Alan Cohen, John Michael Cotte, Lynne M. Gignac, Kenneth Jay Stein, Keith T. Kwietniak, Seshadri Subbanna, Horatio Seymour Wildman, David Earle Seeger, Andrew Herbert Simon
  • Publication number: 20040069648
    Abstract: A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.
    Type: Application
    Filed: October 15, 2002
    Publication date: April 15, 2004
    Applicant: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Hariklia Deligianni, Wilma Jean Horkans, Keith T. Kwietniak, Michael Lane, Sandra G. Malhotra, Fenton Read McFeely, Conal Murray, Kenneth P. Rodbell, Philippe M. Vereecken
  • Patent number: 6592747
    Abstract: Organic addition agents in copper plating baths are monitored by diluting a sample of the bath with sulfuric acid and hydrochloric acid and optionally a cupric salt. The diluting provides a bath having conventional concentrations of cupric ion, sulfuric acid and hydrochloric acid; and adjusted concentrations of the organic addition agents of 1/X of their original values in the sample; where X is the dilution factor. CVS techniques are used to determine concentrations of organic addition agents.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: July 15, 2003
    Assignee: International Business Machines Corporation
    Inventors: Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke
  • Publication number: 20030000850
    Abstract: Organic addition agents in copper plating baths are monitored by diluting a sample of the bath with sulfuric acid and hydrochloric acid and optionally a cupric salt. The diluting provides a bath having conventional concentrations of cupric ion, sulfuric acid and hydrochloric acid; and adjusted concentrations of the organic addition agents of 1/X of their original values in the sample; where X is the dilution factor. CVS techniques are used to determine concentrations of organic addition agents.
    Type: Application
    Filed: June 18, 2001
    Publication date: January 2, 2003
    Inventors: Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke
  • Publication number: 20020027082
    Abstract: A method of reducing etching of a seed layer by a plating solution. Prior to introducing the semiconductor wafer with the seed layer into the plating solution, the etching power of the plating solution is diminished.
    Type: Application
    Filed: October 23, 2001
    Publication date: March 7, 2002
    Inventors: Panayotis C. Andricacos, W. Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Cyprian E. Uzoh
  • Patent number: 6331237
    Abstract: A method of reducing etching of a seed layer by a plating solution. Prior to introducing the semiconductor wafer with the seed layer into the plating solution, the etching power of the plating solution is diminished.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: December 18, 2001
    Assignee: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, W. Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Cyprian E. Uzoh