Patents by Inventor Keith Tabakman

Keith Tabakman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734233
    Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Guowei Xu, Keith Tabakman
  • Publication number: 20200203480
    Abstract: A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 25, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Lin HU, Veeraraghavan S. BASKER, Brian J. GREENE, Kai ZHAO, Daniel JAEGER, Keith TABAKMAN, Christopher NASSAR
  • Publication number: 20200152749
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.
    Type: Application
    Filed: January 15, 2020
    Publication date: May 14, 2020
    Inventors: Hui ZANG, Guowei XU, Keith TABAKMAN, Viraj SARDESAI
  • Patent number: 10580875
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Guowei Xu, Keith Tabakman, Viraj Sardesai
  • Publication number: 20190259619
    Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.
    Type: Application
    Filed: February 22, 2018
    Publication date: August 22, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Guowei Xu, Keith Tabakman
  • Publication number: 20190221650
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.
    Type: Application
    Filed: January 17, 2018
    Publication date: July 18, 2019
    Inventors: Hui ZANG, Guowei XU, Keith TABAKMAN, Viraj SARDESAI
  • Patent number: 10297504
    Abstract: Various novel methods of forming a gate-to-source/drain conductive contact structure and the resulting novel device structures are disclosed. One illustrative method disclosed herein includes performing at least one first etching process to form a recess in a gate structure of a gate of a transistor device so as to expose an innermost surface of a portion of a sidewall spacer positioned adjacent a first sidewall of the gate structure and performing at least one second etching process through at least the recess in the gate structure so as to remove at least a portion of the portion of the sidewall spacer with the exposed innermost surface.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Keith Tabakman, Ruilong Xie
  • Publication number: 20190043758
    Abstract: Various novel methods of forming a gate-to-source/drain conductive contact structure and the resulting novel device structures are disclosed. One illustrative method disclosed herein includes performing at least one first etching process to form a recess in a gate structure of a gate of a transistor device so as to expose an innermost surface of a portion of a sidewall spacer positioned adjacent a first sidewall of the gate structure and performing at least one second etching process through at least the recess in the gate structure so as to remove at least a portion of the portion of the sidewall spacer with the exposed innermost surface.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 7, 2019
    Inventors: Hui Zang, Keith Tabakman, Ruilong Xie
  • Patent number: 10192791
    Abstract: A method of forming a robust low-k sidewall spacer by exposing an upper portion of the spacer to a thermal and plasma treatment prior to downstream processes and resulting device are provided. Embodiments include providing a pair of gates separated by a canyon trench over a substrate, an EPI layer in a bottom of the canyon trench, respectively, and a low-k spacer on each opposing sidewall of the pair; forming a masking layer in a bottom portion of the canyon trench, an upper portion of the low-k spacers exposed; and treating the upper portion of the low-k spacers with a thermal and plasma treatment.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Man Gu, Tao Han, Junsic Hong, Jiehui Shu, Asli Sirman, Charlotte Adams, Jinping Liu, Keith Tabakman
  • Patent number: 9831123
    Abstract: One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: November 28, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Suraj K. Patil, Zhiguo Sun, Keith Tabakman
  • Publication number: 20170287777
    Abstract: One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.
    Type: Application
    Filed: April 5, 2016
    Publication date: October 5, 2017
    Inventors: Suraj K. Patil, Zhiguo Sun, Keith Tabakman
  • Patent number: 9613855
    Abstract: A method that includes, among other things, forming first and second contact openings in a layer of insulating material that respectively expose a portion of first and second source/drain (S/D) regions of first and second transistors that are of the opposite type, forming first, second and third layers of material within each of the first and second contact openings, and forming an implant masking layer that masks the first contact opening while leaving the second contact opening exposed for further processing. The method also includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, removing the implant masking layer and forming a conductive material in both the first and second contact openings so as to define first and second MIS contact structures positioned in the first and second contact openings.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: April 4, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Suraj K. Patil, Zhiguo Sun, Keith Tabakman
  • Patent number: 9536900
    Abstract: A method of manufacturing a semiconductor device, by etching a region of an SOI substrate so that only a portion of the original semiconductor is present above the insulator layer. After etching has occurred, a different semiconductor material is grown in the etched region, and fins are formed. An isolation layer is deposited to a height above that the base semiconductor of the etched region.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: January 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravikumar Ramachandran, Huiling Shang, Keith Tabakman, Henry K. Utomo, Reinaldo A. Vega
  • Publication number: 20150340381
    Abstract: A method of manufacturing a semiconductor device, by etching a region of an SOI substrate so that only a portion of the original semiconductor is present above the insulator layer. After etching has occurred, a different semiconductor material is grown in the etched region, and fins are formed. An isolation layer is deposited to a height above that the base semiconductor of the etched region.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Ravikumar Ramachandran, Huiling Shang, Keith Tabakman, Henry K. Utomo, Reinaldo A. Vega
  • Patent number: 7895008
    Abstract: A method of performing measurement sampling in a production process includes passing a lot through a manufacturing process, employing a set of combinational logistics to determine if sampling is indicated and, if sampling is indicated, establishing a sampling decision. The method further requires querying a set of lot sampling rules to evaluate the sampling decision, evaluating a statistical quality of the process if no lot sampling rules exist, and automatically determining whether the lot passing through the production process requires sampling based on the combinational logistics, statistical quality and lot sampling rules.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gary W. Behm, Yue Li, Malek Ben Salem, Keith Tabakman
  • Patent number: 7751920
    Abstract: A computing system, method, and computer program product facilitates data mining of information, for example image data, relating to a surface of a manufactured product when the manufactured product is processed using a tool relative to which the manufactured product may be randomly oriented. For each manufactured object, data pertaining to the surface is converted into a weight distribution. A rotational axis along which each surface would tend to rotate under the action of gravity with the surface supported at its geometric centroid is determined. The sets of data can then be properly oriented relative to one another for data mining by aligning the rotational axis of each set of data.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Thomas P. Moyer, Keith Tabakman, Brian M. Trapp
  • Publication number: 20090234485
    Abstract: A method of performing measurement sampling in a production process includes passing a lot through a manufacturing process, employing a set of combinational logistics to determine if sampling is indicated and, if sampling is indicated, establishing a sampling decision. The method further requires querying a set of lot sampling rules to evaluate the sampling decision, evaluating a statistical quality of the process if no lot sampling rules exist, and automatically determining whether the lot passing through the production process requires sampling based on the combinational logistics, statistical quality and lot sampling rules.
    Type: Application
    Filed: March 17, 2008
    Publication date: September 17, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gary W. Behm, Yue Li, Malek Ben Salem, Keith Tabakman
  • Publication number: 20080140247
    Abstract: A computing system, method, and computer program product facilitates data mining of information, for example image data, relating to a surface of a manufactured product when the manufactured product is processed using a tool relative to which the manufactured product may be randomly oriented. For each manufactured object, data pertaining to the surface is converted into a weight distribution. A rotational axis along which each surface would tend to rotate under the action of gravity with the surface supported at its geometric centroid is determined. The sets of data can then be properly oriented relative to one another for data mining by aligning the rotational axis of each set of data.
    Type: Application
    Filed: December 8, 2006
    Publication date: June 12, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas P. Moyer, Keith Tabakman, Brian M. Trapp