Patents by Inventor Keith V. Guinn

Keith V. Guinn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9917413
    Abstract: A cooler for diode-laser bars comprises a machined base including a water-input plenum and a water-output plenum, and a top plate on which the diode-laser bars can be mounted. A stack of three etched plates is provided between the base and first plate. The stack of etched plates is configured to provide a five longitudinally spaced-apart rows of eight laterally spaced-apart cooling-channels connected to the water-input and water-output plenums. Water flows in the cooling-channels and in thermal contact with the first plate.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: March 13, 2018
    Assignee: COHERENT, INC.
    Inventor: Keith V. Guinn
  • Publication number: 20170237231
    Abstract: A cooler for diode-laser bars comprises a machined base including a water-input plenum and a water-output plenum, and a top plate on which the diode-laser bars can be mounted. A stack of three etched plates is provided between the base and first plate. The stack of etched plates is configured to provide a five longitudinally spaced-apart rows of eight laterally spaced-apart cooling-channels connected to the water-input and water-output plenums. Water flows in the cooling-channels and in thermal contact with the first plate.
    Type: Application
    Filed: December 13, 2016
    Publication date: August 17, 2017
    Inventor: Keith V. GUINN
  • Patent number: 9546826
    Abstract: A heat transport structure is provided having a structural microtruss wick with a thermal transport medium associated with the microtruss wick for thermal energy transport by fluid and vapor transport between a heat source and a heat sink.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: January 17, 2017
    Assignee: HRL Laboratories, LLC
    Inventors: William B. Carter, Adam F. Gross, Keith V. Guinn, Alan J. Jacobsen, David Kisailus
  • Patent number: 8921702
    Abstract: In one possible implementation, a thermal plane structure includes a non-wicking structural microtruss between opposing surfaces of a multilayer structure and a thermal transport medium within the thermal plane structure for fluid and vapor transport between a thermal source and a thermal sink. A microtruss wick is located between the opposing surfaces and extends between the thermal source and the thermal sink.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: December 30, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: William B. Carter, Peter D. Brewer, Adam F. Gross, Jeffrey L. Rogers, Keith V. Guinn, Alan J. Jacobsen
  • Patent number: 8567049
    Abstract: An electrical assembly (300, 400) includes a power IC such as a MOSFET (112, 412) attached to a substrate module (114, 214). The MOSFET includes a top surface comprising first and second conductive device surfaces (A, B), associated with first and second device ports, and a bottom surface comprising a third conductive device surface C associated with a third device port. A first foil element is bonded to the first conductive device surface(s) A and to each of the first conductive substrate surfaces (A1, A2) and provides a continuous conductive pathway from each conductive surface (A) to each other conductive surface (A) and to each conductive surface (A1, A2). A second foil element is bonded to the second conductive device surface(s) B and to the second conductive substrate surface B1 and provides a continuous conductive pathway from each device conductive surface (B) to the substrate conductive surface (B1).
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: October 29, 2013
    Assignee: Raytheon Company
    Inventor: Keith V. Guinn
  • Patent number: 8349650
    Abstract: A multi-layered semiconductor apparatus capable of producing at least 500 W of continuous power includes at least two device substrates arranged in a stack. Each of the at least two device substrates has a first side and a second side opposite to the first side, and each of the at least two device substrates is configured to produce an average power density higher than 100 W/cm2. A plurality of active devices are provided on the first side of each of the at least two device substrates. The plurality of active devices are radiatively coupled among the at least two device substrates. At least one of the at least two device substrates is structured to provide a plurality of cavities on its second side to receive corresponding ones of the plurality of active devices on the first side of an adjacent one of the at least two device substrates.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: January 8, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: Peter D. Brewer, Keith V. Guinn, Jonathan J. Lynch
  • Patent number: 8080774
    Abstract: A millimeter wave module for providing one pixel having a pixel resolution in a millimeter wave focal plane array includes a horn antenna having a first cross section area less than or equal to the pixel resolution, a detector for detecting the millimeter wave signals received by the horn antenna, the detector mounted in a recess in the horn antenna and having a second cross section area less than or equal to the first cross section area, and a video output adapter connected to the horn antenna and electrically connected to the detector for providing a connection from the detector, the video output adapter having a third cross section area less than or equal to the first cross section area.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: December 20, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: Keith V. Guinn, James H. Schaffner, Jonathan Lynch
  • Publication number: 20110278350
    Abstract: An electrical assembly (300, 400) includes a power IC such as a MOSFET (112, 412) attached to a substrate module (114, 214). The MOSFET includes a top surface comprising first and second conductive device surfaces (A, B), associated with first and second device ports, and a bottom surface comprising a third conductive device surface C associated with a third device port. A first foil element is bonded to the first conductive device surface(s) A and to each of the first conductive substrate surfaces (A1, A2) and provides a continuous conductive pathway from each conductive surface (A) to each other conductive surface (A) and to each conductive surface (A1, A2). A second foil element is bonded to the second conductive device surface(s) B and to the second conductive substrate surface B1 and provides a continuous conductive pathway from each device conductive surface (B) to the substrate conductive surface (B1).
    Type: Application
    Filed: July 21, 2011
    Publication date: November 17, 2011
    Inventor: Keith V. Guinn
  • Patent number: 8009439
    Abstract: An electrical assembly (300, 400) includes a power IC such as a MOSFET (112, 412) attached to a substrate module (114, 214). The MOSFET includes a top surface comprising first and second conductive device surfaces (A, B), associated with first and second device ports, and a bottom surface comprising a third conductive device surface C associated with a third device port. A first foil element is bonded to the first conductive device surface(s) A and to each of the first conductive substrate surfaces (A1, A2) and provides a continuous conductive pathway from each conductive surface (A) to each other conductive surface (A) and to each conductive surface (A1, A2). A second foil element is bonded to the second conductive device surface(s) B and to the second conductive substrate surface B1 and provides a continuous conductive pathway from each device conductive surface (B) to the substrate conductive surface (B1).
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: August 30, 2011
    Assignee: Raytheon Company
    Inventor: Keith V. Guinn
  • Patent number: 7956381
    Abstract: A multi-layered semiconductor apparatus capable of producing at least 500 W of continuous power includes at least two device substrates arranged in a stack. Each of the at least two device substrates has a first side and a second side opposite to the first side, and each of the at least two device substrates is configured to produce an average power density higher than 100 W/cm2. A plurality of active devices are provided on the first side of each of the at least two device substrates. The plurality of active devices are radiatively coupled among the at least two device substrates. At least one of the at least two device substrates is structured to provide a plurality of cavities on its second side to receive corresponding ones of the plurality of active devices on the first side of an adjacent one of the at least two device substrates.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: June 7, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: Peter D. Brewer, Keith V. Guinn, Jonathan J. Lynch
  • Publication number: 20090140427
    Abstract: An electrical assembly (300, 400) includes a power IC such as a MOSFET (112, 412) attached to a substrate module (114, 214). The MOSFET includes a top surface comprising first and second conductive device surfaces (A, B), associated with first and second device ports, and a bottom surface comprising a third conductive device surface C associated with a third device port. A first foil element is bonded to the first conductive device surface(s) A and to each of the first conductive substrate surfaces (A1, A2) and provides a continuous conductive pathway from each conductive surface (A) to each other conductive surface (A) and to each conductive surface (A1, A2). A second foil element is bonded to the second conductive device surface(s) B and to the second conductive substrate surface B1 and provides a continuous conductive pathway from each device conductive surface (B) to the substrate conductive surface (B1).
    Type: Application
    Filed: November 30, 2007
    Publication date: June 4, 2009
    Applicant: RAYTHEON COMPANY
    Inventor: Keith V. Guinn
  • Patent number: 6677832
    Abstract: An electrical connecting element is disclosed comprised of a dielectric substrate having two conductor paths disposed on opposite sides and being substantially aligned with one another. The electrical connecting element employs differential-mode signaling such that the first conductor path carries a signal of opposite polarity to the second conductor path. A virtual ground exists between the differential + and − lines that permits an otherwise “groundless” differential transmission line. The substantial alignment of the first and second conductor paths improves the space constraints, relative to conventional electrical connecting elements. The characteristic impedance of the disclosed differential transmission line depends on the width of the trace lines the thickness of the dielectric substrate.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: January 13, 2004
    Assignee: Lucent Technologies Inc.
    Inventors: Keith V. Guinn, Louis Thomas Manzione, Ming-Ju Tsai, Hui Wu
  • Patent number: 6421011
    Abstract: A non-conductive frame supports the resonators in a patch antenna assembly. The frame supports the resonators without making holes in the resonators and thereby avoids the problem of creating unwanted electric field polarizations. Additionally, the frame grasps the resonators in areas of low current density and thereby avoids creating additional disturbances in the radiation pattern. The frames may also include posts that are used to attach the frames to the feedboard without using additional components such as screws.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: July 16, 2002
    Assignee: Lucent Technologies Inc.
    Inventors: Maarten Van Egmond, Keith V. Guinn, Stelios Papatheodorou, Edward Bryan Roberts, Ming-Ju Tsai, Michael A. Zimmerman
  • Patent number: 6407704
    Abstract: A patch antenna's resonators are supported by a non-conductive frame. The frame supports the resonators without making holes in the resonators and thereby avoids the problem of creating unwanted electric field polarizations. Additionally, the frame grasps the resonators in areas of low current density and thereby avoids creating additional disturbances in the radiation pattern. In one embodiment of the invention, the frame includes a perimeter lip that snaps over the edges of the feedboard and thereby attaches the frame to the feedboard.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: June 18, 2002
    Assignee: Lucent Technologies Inc.
    Inventors: John Philip Franey, Keith V. Guinn, Louis Thomas Manzione, Ming-Ju Tsai
  • Patent number: 6404389
    Abstract: An inexpensive, easy to assemble patch antenna is disclosed where unwanted polarizations in the transmitted RF energy are minimized. A feedboard, spacer and resonator are held in a compressed relationship by two halves of the antenna housing. The spacer is a thermo-formed sheet with semi-spherical spacers. The spacers have a height that provides the desired spacing between the feedboard and the resonator.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: June 11, 2002
    Assignee: Lucent Technologies Inc.
    Inventors: John Philip Franey, Keith V. Guinn, Louis Thomas Manzione, Ming-Ju Tsai
  • Patent number: 6232923
    Abstract: The conductive layers corresponding to a patch antenna are formed on a single substrate, as by printing a conductive ink. The substrate is in the form of an elongated, non-conductive, flexible sheet with the consecutive antenna layers printed thereon side-by-side. The layers of the antenna can then be brought into superposed alignment by appropriate folding of the sheet. The non-conductive rectangles can be maintained in spaced alignment to the cut-outs by placing a porous non-conductive block of spacing material therebetween. In a preferred embodiment the assembled structure has the various layers bonded together.
    Type: Grant
    Filed: November 11, 1999
    Date of Patent: May 15, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Keith V. Guinn, George John Shevchuk, Yiu-Huen Wong
  • Patent number: 5877032
    Abstract: The present invention is directed to a process for device fabrication in which a pattern is transferred from a photoresist mask into an underlying layer of silicon dioxide. A plasma containing a fluorocarbon gas is used to etch the pattern into the underlying silicon dioxide layer. The plasma is monitored using optical emission spectroscopy to effect control of the etch process. The optical emission is monitored at select wavelengths. To control the process based on an observation of photoresist etch rate, two wavelengths are monitored. One is associated with a species that is produced by the interaction between the photoresist and the plasma, and one is associated with a species related to the plasma intensity.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: March 2, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Keith V. Guinn, Susan Clardy McNevin