Abstract: A configuration for a carbon nanotube (CNT) based memory device can include multiple CNT elements in order to increase memory cell yield by reducing the times when a memory cell gets stuck at a high state or a low state.

Abstract: A desired current through a carbon nano tube (CNT) element of a CNT memory device can be controlled by a wordline voltage, and a voltage on the CNT common node can be held constant. The common node can be constant at a source voltage if a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) is used in the CNT memory device, or the common node can be constant at a supply voltage if an n-channel MOSFET is used in the CNT memory device.

Abstract: A configuration for a carbon nanotube (CNT) based memory device can include multiple CNT elements in order to increase memory cell yield by reducing the times when a memory cell gets stuck at a high state or a low state.

Abstract: A desired current through a carbon nano tube (CNT) element of a CNT memory device can be controlled by a wordline voltage, and a voltage on the CNT common node can be held constant.

Abstract: A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.

Abstract: Behaviors of a transistor during a dose rate event can be modeled using a circuit simulation software package. A subcircuit model replaces a transistor in a circuit design to be simulated. The subcircuit model can be in the form of a schematic-based representation or a netlist. The subcircuit model provides a model of a source junction and a drain junction in the transistor during the dose rate event. The subcircuit model also includes the size of the transistor being replaced and the dose rate of the dose rate event. Once the transistor is replaced with the subcircuit model, a dose rate simulation may be performed to determine the dose rate hardness of the circuit design.

Abstract: A hardening system includes a data storage device having a data input, a clock input, a data node Q, and a data complement node QN. The data storage device provides drive to the data node Q and the data complement node QN. A hardening circuit includes first, second, third, fourth, and fifth transistor circuits. The first and second transistor circuits form a first node therebetween, and the first transistor circuit prevents the data node Q from changing states in the presence of radiation. The third and fourth transistor circuits form a second node therebetween, and the third transistor circuit prevents the data complement node QN from changing states in the presence of radiation. The first node is coupled to the third transistor circuit, and the second node is coupled to the first transistor circuit. The fifth transistor circuit prevents the first and second nodes from floating.

Abstract: A hardening system includes a data storage device having a data input, a clock input, a data node Q, and a data complement node QN. The data storage device provides drive to the data node Q and the data complement node QN. A hardening circuit includes first, second, third, fourth, and fifth transistor circuits. The first and second transistor circuits form a first node therebetween, and the first transistor circuit prevents the data node Q from changing states in the presence of radiation. The third and fourth transistor circuits form a second node therebetween, and the third transistor circuit prevents the data complement node QN from changing states in the presence of radiation. The first node is coupled to the third transistor circuit, and the second node is coupled to the first transistor circuit. The fifth transistor circuit prevents the first and second nodes from floating.

Abstract: A hardening circuit is provided for an integrated circuit which includes a data state reinforcing feedback path having a data node Q and a data complement node QN. A first hardening transistor is coupled between a rail and the data node Q, and a second hardening transistor coupled between the rail and the data complement node QN. The first and second hardening transistors provide additional drive to the data node Q and the data complement node QN. Gate controls operate the first and second hardening transistors and provide full rail drive to SEU sensitive nodes.

Abstract: A hardening circuit is provided for an integrated circuit which includes a data state reinforcing feedback path having a data node Q and a data complement node QN. A first hardening transistor is coupled between a rail and the data node Q, and a second hardening transistor coupled between the rail and the data complement node QN. The first and second hardening transistors provide additional drive to the data node Q and the data complement node QN. Gate controls operate the first and second hardening transistors and provide full rail drive to SEU sensitive nodes.

Abstract: A method for forming a frontside substrate contact on a Silicon-On-Insulator wafer in the presence of planarized contact dielectric is described. The method offers the improvement of reducing the etch selectivity requirements while allowing simultaneous etching and metallization of gate, source, drain and substrate contacts.

Abstract: A multi-purpose device that can serve as either a resistor, MOSFET or JFET is disclosed. The resistor is formed by selecting a first metal interconnect configuration, the MOSFET is formed by selecting a second metal interconnect configuration, and the JFET is formed by selecting a third metal interconnect configuration. Because of the dual transistor/resistor nature of this device, the density of a typical gate array that uses resistors may be increased. In addition, and because no special processing is typically required, the device may be desirable for use in other types of structures such as standard cells and custom logic.

Abstract: A SEU hardening circuit for use with a data storage circuit is described. The SEU hardening circuit may use a transmission gate to provide full rail drive during a write operation. The SEU hardening circuit may also be configured so that the transistors of the SEU hardening circuit are not susceptible to parasitic bipolar turn-on particularly during a radiation event, which can increase the SEU protection provided by the circuit.

Abstract: A CMOS output driver circuit with p-channel substrate tracking provides an output driver to full power supply voltage. The circuit is especially useful as a redundant circuit where its power supply connection is connected to ground and the circuit is kept in unbiased storage until it is needed.

Abstract: A radiation resistant random access memory cell which has a coupling circuit between a storage node of a first CMOS pair and a gate node of a second CMOS pair. The coupling circuit is controlled by a word line and provides a first resistive element between the storage node and the body of the coupling circuit and a second resistive element between the gate node and the body of the coupling circuit.

Abstract: A plurality of memory cells arrayed in columns with the memory cells within a column connected between precharged first and second output lines. An input line selects a memory cell within a volume causing the first output line to be pulled to a first voltage when the cell is programmed a true and causing the second output line to be pulled to a first voltage when the cell is programmed a "complement". A pair of cross-coupled transistors connected between the first and second output lines of a column causes the second output line to be maintained at the precharged voltage when programmed a "true" and causes the first output line to be maintained at a precharged voltage when the cell is programmed a "complement".

Abstract: A plurality of single transistor memory cells arrayed in columns with the memory cells within a column connected to one or the other of precharged first and second output lines. An input line connected to the gate of the single transistor causes the first output line to be pulled to a first voltage when the cell is programmed a "true" and to be pulled to a second voltage when the cell is programmed a "complement". A pair of cross-coupled transistors connected between the first and second output lines of a column cause the second output line to be maintained at the precharged voltage when programmed a "true" and causes the first output line to be maintained at a precharged voltage when programmed a "complement".

Abstract: A fuse status detection circuit for determining the conduction of fuses used in integrated circuits is disclosed based on a flip-flop circuit containing the fuses which is set to an initial state during operation.

Abstract: A memory system having voltage level circuit switching portions operated between signal lines stabilized by additional capacitance.

Abstract: A semiconductor capacitance transducer includes adjoining integrated sensor and reference capacitance transducers formed from silicon wafers. The transducers are parallel plate transducers which are structurally the same except that one plate of the sensor transducer is a thin force sensing diaphragm which deflects in response to selected environmental phenomena while the corresponding plate of the reference transducer is adapted to deform in response to some, but not all, of the selected environmental phenomena. By comparing the capacitance of the transducers, the effects of the phenomena which deform the reference transducer can be distinguished from the effects of the phenomena which do not deform the reference transducer. A particular application of the present invention allows thermal effects on the sensor transducer to be distinguished from the effects of pressure.