Abstract: A multi-layer semiconductor device includes at least a first semiconductor structure and a second semiconductor structure, each having first and second opposing surfaces. The second semiconductor structure includes a first section and a second section, the second section including a device layer and an insulating layer. The second semiconductor structure also includes one or more conductive structures and one or more interconnect pads. Select ones of the interconnect pads are electrically coupled to select ones of the conductive structures. The multi-layer semiconductor device additionally includes one or more interconnect structures disposed between and coupled to select portions of second surfaces of each of the first and second semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes a substrate joining layer disposed between and coupled to the second surface of a first one of the at least two substrate layers and the first surface of a second one of the at least two substrate layers. The substrate joining layer includes at least one integrated circuit (IC) structure disposed between the first and second surfaces of said substrate joining layer. A corresponding method for fabricating a semiconductor structure is also provided.

Abstract: In a system for aligning at least two semiconductor structures for coupling, an alignment device includes a mounting structure having at least first and second opposing portions. The alignment device also includes a first mounting portion movably coupled to the first portion of the mounting structure, the first mounting portion configured to couple to a first surface of a first semiconductor structure. The alignment device additionally includes a second mounting portion movably coupled to the second portion of the mounting structure, the second mounting portion configured to couple to a second surface of a second semiconductor structure. The alignment device further includes one or more imaging devices disposed above at least one of the first and second mounting portions of the alignment device, the imaging devices configured to capture and/or or detect alignment marks in at least the first semiconductor structure.

Abstract: In a system for aligning at least two semiconductor structures for coupling, an alignment device includes a mounting structure having at least first and second opposing portions. The alignment device also includes a first mounting portion movably coupled to the first portion of the mounting structure, the first mounting portion configured to couple to a first surface of a first semiconductor structure. The alignment device additionally includes a second mounting portion movably coupled to the second portion of the mounting structure, the second mounting portion configured to couple to a second surface of a second semiconductor structure. The alignment device further includes one or more imaging devices disposed above at least one of the first and second mounting portions of the alignment device, the imaging devices configured to capture and/or or detect alignment marks in at least the first semiconductor structure.

Abstract: A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes a substrate joining layer disposed between and coupled to the second surface of a first one of the at least two substrate layers and the first surface of a second one of the at least two substrate layers. The substrate joining layer includes at least one integrated circuit (IC) structure disposed between the first and second surfaces of said substrate joining layer. A corres ponding method for fabricating a semiconductor structure is also provided.

Abstract: A multi-layer semiconductor device includes at least a first semiconductor structure and a second semiconductor structure, each having first and second opposing surfaces. The second semiconductor structure includes a first section and a second section, the second section including a device layer and an insulating layer. The second semiconductor structure also includes one or more conductive structures and one or more interconnect pads. Select ones of the interconnect pads are electrically coupled to select ones of the conductive structures. The multi-layer semiconductor device additionally includes one or more interconnect structures disposed between and coupled to select portions of second surfaces of each of the first and second semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: A method of creating plastically deformed devices which have a three dimensional aspect. Micromechanical structures are created from a material which is plastically deformable and then a section of the structure is bent to an out-of-plane position and can be maintained there without being supported by other mechanical devices such as latches or hinges. The bending of the structures may be done mechanically, by electrostatic forces or by magnetic forces. The bending can also be done in a batch mode where a plurality of devices are bent at the same time as part of the same process. Fuses can be utilized to allow only a predetermined number of devices to be bent in batch mode. The fuses are later blown, thereby providing a plurality of devices which are relatively parallel to the substrate as well as a plurality of devices which are generally out-of-plane with respect to the substrate.

Abstract: An interconnection device is disclosed for providing electrical connection between two conducting elements that requires less applied force than a standard ohmic connection device of the same connection area. A surface of at least a first conducting element includes a plurality of atomically sharp projections for creating a strong electric field near the tip of each projection, each projection being disposed within a locally depressed portion of an insulating layer that serves to maintain a space between each tip and a second conducting element that contacts the insulating layer. The strong electric field at each tip induces a variety of conduction modes each contributing to an aggregate current flow from the first conducting element to the second. In an alternate embodiment, a plurality of projections are disposed on the peaks and valleys of a rough surface without an insulating layer, the projections providing a variety of conduction modes.

Abstract: An interconnection device for providing electrical connection between two separable conducting elements that requires less applied force than a standard ohmic connection device of the same connection area includes a surface of at least a first conducting element that includes a plurality of atomically sharp projections for creating a strong electric field near the tip of each projection, each projection being disposed within a locally depressed portion of an insulating layer that serves to maintain a space between each tip and a second conducting element that contacts the insulating layer. The strong electric field at each tip induces a variety of conduction modes each contributing to an aggregate current flow from the first conducting element to the second. In an alternate embodiment, a plurality of projections are disposed on the peaks and valleys of a rough surface without an insulating layer, the projections providing a variety of conduction modes.

Abstract: An interconnection device is disclosed for providing electrical connection between two conducting elements that requires less applied force than a standard ohmic connection device of the same connection area. A surface of at least a first conducting element includes a plurality of atomically sharp projections for creating a strong electric field near the tip of each projection, each projection being disposed within a locally depressed portion of an insulating layer that serves to maintain a space between each tip and a second conducting element that contacts the insulating layer. The strong electric field at each tip induces a variety of conduction modes each contributing to an aggregate current flow from the first conducting element to the second. In an alternate embodiment, a plurality of projections are disposed on the peaks and valleys of a rough surface without an insulating layer, the projections providing a variety of conduction modes.