Abstract: This invention features a method of simultaneously conducting simulation testing of a plurality of simulated device designs using cycle-based software which is capable of simultaneously executing a number of simulation tests along separate test pathways for each simulated device. The method is appropriate for situations in which the simulated device designs each comprise essentially identical sequences of boolean instructions. The method contemplates designating a single bit location of a multiple-word memory device for each test of each simulated device. As the test progress, the results of each test are stored in the appropriate designated bit location for such test. This allows a total number of simultaneous tests equal to the number of bits available in the words making up the memory of the memory device.

Abstract: Methods of speeding error analysis of electronic devices under test using simulation software that has the capability of simultaneously executing up to 32 tests on one image of the design model. One embodiment of the method contemplates executing the tests staggered in time so that a larger portion of the test is available for examination and execution at any given time. This allows errors to be found more quickly. Another embodiment contemplates more quickly testing a device initialization sequence by randomly establishing values for each state device, separately for each of the 32 tests, running the simulation, and then determining whether the state device values converge.