Patents by Inventor Keizo Azuma

Keizo Azuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110173412
    Abstract: A memory protection method includes setting a memory area in at least one address setting register; setting a trap type in a trap type setting register corresponding to the address setting register; generating a trap of the trap type set in the trap type setting register in accordance with an access request to the memory area set at the address setting register; setting a size of an inaccessible area in a memory; allocating, in accordance with a memory allocation request from an application, a memory area to the application as an accessible area and an inaccessible area having the inaccessible area size right after the accessible area; setting the inaccessible area in a first address setting register and a first trap type in a first trap type setting register; and generating a memory image of the application and closing the application when a trap of the first trap type occurred.
    Type: Application
    Filed: March 22, 2011
    Publication date: July 14, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Ryo TABEI, Hiroshi KONDO, Hiroyuki IZUI, Keizo AZUMA
  • Patent number: 7117397
    Abstract: If a failure is detected in a system, it is automatically judged which operation mode should be selected, a system-down mode or a dynamic degeneracy mode. If a failed device is severed from the system, the severance of the device is reported by making a device control unit access the device or changing the state of the device.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: October 3, 2006
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kondo, Keizo Azuma