Abstract: To improve data storage efficiency in a video display system having a video data memory (4) data for display is read out from the memory in a time shared manner. Addressing of the memory is controlled by an address multiplexer (7) in turn controlled by an address converting circuit (21) that generates, successively, memory addresses and memory addresses modified by an offset value.

Abstract: A video display control unit controls characters to be displayed on a sequential scanning display unit (4). Namely, it reads address-specifying information and attribute information from a video memory (5) along scanning sequence of a screen in a continuous and address-unit time-divisional manner on the basis of address signals from a memory address counter (6). The read attribute information is outputted on a multiplex bus (42) through a gate (34) and delayed by a predetermined period by a pipeline register (40) to be supplied to a video signal encoder (18). The read address information is supplied to a character generator (16) so that character information is read from the character generator (16). The character information is outputted on the multiplex bus (42) through a gate (36) and delayed by a predetermined period in a pipeline register (38) to be supplied to the video signal encoder (18).