Patents by Inventor Keizo Hirayama

Keizo Hirayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6133617
    Abstract: Disclosed is a high breakdown voltage semiconductor device comprising a semiconductor substrate, an active layer consisting of a high resistivity semiconductor layer of a first conductivity type formed on the substrate with an insulating layer interposed therebetween, a first impurity region of the first conductivity type formed within the active layer, a second impurity region of a second conductivity type formed within the active layer, a third impurity region of the second conductivity type formed within the second impurity region and having a high impurity concentration, a first electrode being in ohmic contact with the first impurity region and the fourth impurity region, and a second electrode being in Schottky contact with the second impurity region and in ohmic contact with the third impurity region.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: October 17, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keizo Hirayama, Hideyuki Funaki, Fumito Suzuki, Akio Nakagawa
  • Patent number: 5982015
    Abstract: Disclosed is a high breakdown voltage semiconductor device comprising a semiconductor substrate, an active layer consisting of a high resistivity semiconductor layer of a first conductivity type formed on the substrate with an insulating layer interposed therebetween, a first impurity region of the first conductivity type formed within the active layer, a second impurity region of a second conductivity type formed within the active layer, a third impurity region of the second conductivity type formed within the second impurity region and having a high impurity concentration, a first electrode being in ohmic contact with the first impurity region and the fourth impurity region, and a second electrode being in Schottky contact with the second impurity region and in ohmic contact with the third impurity region.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: November 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keizo Hirayama, Hideyuki Funaki, Fumito Suzuki, Akio Nakagawa
  • Patent number: 4433229
    Abstract: An electrode roll for resistance welding comprising a fixed portion which has a disc portion at the longitudinal center part of a shaft where the disc portion and the shaft are at right angles to each other; a rotary portion which surrounds the fixed portion and has inner surfaces forming two side gaps facing the two side surfaces of the disc portion and a peripheral gap facing the peripheral surface of the disc portion, respectively; and a conductive liquid metal received in each of the gaps, where the peripheral gap is so narrow that the above conductive liquid metal may be pulled up along the gap to fill the same when the above rotary portion rotates, and the side gaps are substantially wider than the peripheral gap.
    Type: Grant
    Filed: November 16, 1981
    Date of Patent: February 21, 1984
    Assignee: Daiwa Can Company, Limited
    Inventors: Yonekichi Morikawa, Toshio Shimizu, Eiichi Yoshida, Tsuyoshi Konagaya, Keizo Hirayama